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Harshit Jaiswal

Harshit Jaiswal

Student

Followers of Harshit Jaiswal446 followers
location of Harshit JaiswalBengaluru, Karnataka, India

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  • Timeline

  • About me

    Senior Principal Application Engineer at Cadence Design Systems

  • Education

    • JB Academy

      1995 - 2008
      Senior secondary

      1. Represented my school in COFAS-International Computer Olympiad for Fair and Seminar.2. Bagged a 1st Rank in senior science exhibition at a school level.

    • Birla Institute of Technology and Science, Pilani

      2021 - 2023
      Master of Technology - MTech Microelectronics 9.00

    • Indian Institute of Information Technology

      2009 - 2013
      B.Tech Electronics and Communication Engineering 9.00

      Activities and Societies: 1. Elected as the Head of the ALC (Audio, Lights and Camera) Committee in the 4th National Science conclave- an official gathering of noble laureate and eminent scientist. 2. Organised an event named ELECTROMANIAC- an instant circuit designing competition in college technical cum cultural festival named Effervesence MMXI. 1. Secured a 1st Rank in MANGIX-a circuit designing competition in college technical cum cultural festival named Effervesence MMX.2. Secured a 1st Rank in Techno-Fault-a circuit designing and debugging competition in college technical cumcultural festival named Effervesence MMXI.3. Secured a 3rd Rank in Stegolica-an online steganographic event in college technical cum cultural festival named Effervesence MMXI

  • Experience

    • Indian Institute of Information Technology,Allahabad

      Jul 2009 - Jun 2013
      Student

    • Qualcomm

      May 2012 - Jul 2012
      Summer intern

      i.Studied the fundamental concepts of DFT ii. Automated the Domain Analysis process iii. Generated ATPG patterns using Tetramaxiv. Automated the quality check for different modes in hard macros.

    • Qualcomm

      Jul 2013 - May 2016

      Responsible for handling chip top PNR runs with full tile flow and closing all the signoff checks (FV,CLP,PV,IR,PDNA,Timing) Handling all tasks from DFT netlist input to GDS by working on various physical design tools and provide a timing clean, DRC clean, FV, CLP, PDNA clean database 1.Responsible for handling chip top PNR runs with full tile flow and closing all the signoff checks (FV,CLP,PV,IR,PDNA,Timing) 2. Handling all tasks from DFT netlist input to GDS by working on various physical design tools and provide a timing clean, DRC clean, FV, CLP, PDNA clean database

      • Engineer

        Jul 2015 - May 2016

      • Associate Engineer

        Jul 2013 - Jun 2015

    • Cadence Design Systems

      May 2016 - now

      1. Working on Focus accounts for customer support group.2. Supporting Innovus implementation solution either by onsite or by remote VNC3. Acting as a point contact for Broadcom, Broadcom_APD and ADI4. Supporting knowledge development initiative for placement and its optimization.5. Ramping up application engineers and deploying them in Focus support initiative.6. Delivered trainings to the various customer for innovus and common_ui.

      • Senior Principal Application Engineer

        Jul 2024 - now

      • Principal Support Application Engineer

        Jul 2021 - now

      • Lead Support Application Engineer

        Jul 2018 - Jun 2021

      • Senior Application Support Engineer

        May 2016 - Jun 2018

  • Licenses & Certifications

  • Volunteer Experience

    • Volunteer

      Issued by Indian Institute Of Information Technology on Dec 2012
      Indian Institute Of Information TechnologyAssociated with Harshit Jaiswal

    • Coordinator

      Issued by Indian Institute Of Information Technology on Oct 2013
      Indian Institute Of Information TechnologyAssociated with Harshit Jaiswal