
Jitendra Kolhe
Senior Programmer

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About me
Senior System Software Engineer at NVIDIA Graphics Pvt. Ltd.
Education

Mumbai University - R.A.I.T
1998 - 2002B.E. Computer Science
Experience

Indiagames Ltd.
Jul 2003 - Jun 2006Senior ProgrammerDeveloped Applications, 2D & 3D Games, 3D Cross Platform Game Engine for Mobile handsets using BREW and Symbian Platforms.

Tata Consultancy Services
Jul 2006 - Nov 2010VSE-NCGL Team (Versatile Service Engine - Nortel Carrier Grade Linux Team - ATCA Compliant Platform) - Module Lead• Worked on support cases which involved debugging Kernel Oops, panics on i386, PPC, PPC64 & MIPS architectures. • Modified Linux kernel to develop wrappers around existing spinlock functionality, which will store module name and PID which has already acquired lock. This information is dumped with NMI watchdog is fired when CPU is hung for more than 5 seconds, due to double lock. • Enhance ethtool to calculate good packet received rate (e1000 driver). Show less
Assistant Consultant
Jan 2010 - Nov 2010IT Analyst
Jul 2007 - Dec 2009Assistant Systems Engineer
Jul 2006 - Jun 2007

Hewlett Packard Enterprise
Nov 2010 - Mar 2020Dot Product Engine (DPE) - Neural Network Accelerator• Designed and implemented components like Loader, Compiler Toolchain, Scheduler in software stack for the accelerator.• Worked on developing software emulator, used to test in-house compiler and estimate performance of a given NN model on accelerator.• Emulated the accelerator on QEMU, used to test other components in sw stack like the driver, loader and assembler components.• Currently engaged in developing compiler backend for convolution operation for the accelerator. Show less QEMU• Addressed few bottlenecks in QEMU to improve start-up time of QEMU-KVM guest by ~25X for Fat guests.HP-UX vPars and Integrity VM - (HPVM hypervisor)• Designed and developed the Locality Virtualization feature which was a requirement for enabling Online Migration of HP-UX vPars.• Modified ACPI namespaces presented to guest OS (HP-UX) to add support for online addition and deletion of Virtual CPUs for the Guest. Implemented Pagetable, TLB cache clean-ups required while deleting the Virtual CPU.• Added support for 32 Virtual CPU's for HPVM guests, there by identifying and addressing scaling issues and in process improving performance of HPVM guest by 4x. Show less
Expert Technologist
Aug 2018 - Mar 2020Senior Systems Specialist
Mar 2013 - Jul 2018System Specialist
Nov 2010 - Feb 2013

NVIDIA
Mar 2020 - nowSenior System Software Engineer
Licenses & Certifications

Leading without Formal Authority
LinkedInNov 2019
Decision-Making Strategies
LinkedInNov 2019
Managing Team Creativity
LinkedInNov 2019
Collaboration Principles and Process
LinkedInNov 2019
Developing Business Acumen
LinkedInNov 2019
Learning Design Thinking: Lead Change in Your Organization
LinkedInNov 2019
Thought Leadership (2012)
LinkedInNov 2019
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