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Bhargav S

Bhargav S

Business Automation Intern

Followers of Bhargav S4000 followers
location of Bhargav SBengaluru, Karnataka, India

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  • Timeline

  • About me

    ASIC Engineer at NVIDIA | Ex-Synopsoid | AI Enthusiast | Jack of all Electronics Domains

  • Education

    • Base Education

      2016 - 2018
      PUC PCME 97.33%

      Activities and Societies: Pure science stream training and applied lab exposure Was a part of the toppers batch run at the Base educational services Pvt LTD Basavangudi

    • Hymamshu Jyothi Kala Peetha

      2006 - 2016
      SSLC State syllabus 98.88%

      Activities and Societies: IT quizes, Science Fairs, Badminton, Volley Ball, Table tennis Was enithusiastic about science and maths and also played sports

    • B. M. S. College of Engineering

      2018 - 2022
      Bachelor of Engineering - BE Electrical, Electronics and Communications Engineering 9.6

    • B. M. S. College of Engineering

      2018 - 2022
      Bachelor of Engineering - BE Electrical, Electronics and Communications Engineering 9.62

  • Experience

    • SARCI.in

      Jul 2020 - Apr 2021
      Business Automation Intern

      I worked on developing an autonomous software for parsing textual documents in any format (readable or non-readable) to extract necessary data fields. It is built using a python backend and JavaScript based User-Interface. It can handle various kinds of document structures and has been rigorously tested.The use cases include tax invoice parsing, bank document parsing and other company document parsing for automatic data entry.

    • Honeywell

      Apr 2021 - Jun 2021
      Software Engineer Intern

      I worked on an IOT based project under the Connected Buildings branch of Honeywell Organisation. I automated the Smoke Testing of Samba Application using Selenium.

    • Synopsys Inc

      Feb 2022 - Jan 2024

      As a part of the USB Design team, I was responsible for the following:1. Design Ownership: I work on the Link and Protocol Adapter modules of the controller where I work on incremental design enhancements, simulation debug, assertion modelling and doc updates.2. Tool Exposure: I have extensively worked on Spyglass and VC Spyglass tools for Lint, CDC and RDC enhancements. I maintain the controller's compliance with system-level RAL, synthesis tool flows, and Synopsys TCM tool. I have also been exposed to Synthesis tools like Design Compiler, Fusion Compiler and Power analysis tools like VCLP.Apart from the technical exposure, I have also been trained on Soft Skills and am also an active volunteer in Nex-GEN ERG and CSR groups of Synopsys Show less

      • ASIC Design Engineer I

        Jul 2022 - Jan 2024

      • Technical Intern

        Feb 2022 - Jul 2022

    • NVIDIA

      Jan 2024 - now
      ASIC Design Engineer II

      As as an ASIC Engineer in the Central Low Power Team of Nvidia,1. I work on designing low-power features for the most advanced GPU and CPU products.2. I work on leveraging Formal Verification for Power-aware verification.

  • Licenses & Certifications

  • Honors & Awards

    • Awarded to Bhargav S
      Arctic Code Vault Contributor github Sep 2020 Contributed to Github 2020 Archive Program.