Naresh Babu

Education

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  Takshila Institute of VLSI Technologies -Apprenticeship

  2023 - 2023

  Physical Design

  As a Physical Design Engineer Trainee at Takshila Institute of VLSI Technologies, I immersed myself in the dynamic realm of VLSI design. Under the mentorship of seasoned professionals, I gained hands-on experience in CMOS technology, digital electronics, and various aspects of physical design. My responsibilities included floorplanning, power planning, placement, clock tree synthesis, routing, and utilizing TCL for automation. I actively participated in Design Rule Checking (DRC) processes and… Show more As a Physical Design Engineer Trainee at Takshila Institute of VLSI Technologies, I immersed myself in the dynamic realm of VLSI design. Under the mentorship of seasoned professionals, I gained hands-on experience in CMOS technology, digital electronics, and various aspects of physical design. My responsibilities included floorplanning, power planning, placement, clock tree synthesis, routing, and utilizing TCL for automation. I actively participated in Design Rule Checking (DRC) processes and performed Statistical Timing Analysis (STA) to ensure robustness and efficiency in chip design. This enriching experience honed my technical skills and provided me with invaluable insights into the intricacies of semiconductor design methodologies. Show less

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  APSWREIS (B) JR. COLLEGE

  2017 - 2019

  Intermediate MPC 9.8
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  ST. MARY'S HIGH SCHOOL (EM)

  2016 - 2017

  SSC 8.7
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  Jawaharlal Nehru Technological University

  2019 - 2023

  Bachelor of Technology - BTech Electronics and Communications Engineering 7.0