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Manish Garg

Manish Garg

Design Engg

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location of Manish GargDelhi, India

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  • Timeline

  • About me

    Serdes Design at Cadence Design Systems

  • Education

    • Netaji Subhas Institute of Technology

      2002 - 2006
      Bachelor of Engineering (B.E) Electrical, Electronics and Communications Engineering

      B.E. in Electronics & Communication

  • Experience

    • Texas Instruments

      Jul 2006 - Dec 2007
      Design Engg

      Circuit Designing of IO cells

    • STMicroelectronics

      Dec 2007 - May 2008
      Design Engineer

      Circuit Design of High Speed Serial Links

    • Texas Instruments

      May 2008 - Apr 2009
      Design Engg

      Circuit Designing of IOs for wireless

    • STMicroelectronics

      Jul 2012 - Mar 2015
      Technical Lead

      Circuit Designing of High Speed Links

    • Synopsys Inc

      Mar 2015 - Mar 2017
      AM&S Design Engg SR1

      Analog & Mixed Signal Circuit Designmajorly hdmi

    • UST Global --> Intel

      Mar 2017 - Apr 2018
      Execution Manager

    • STMicroelectronics

      Apr 2018 - Oct 2020
      Staff Engineer

    • Cadence Design Systems

      Oct 2020 - now
      Analog and Mix Signal Design

  • Licenses & Certifications