CHANGSEON JO

Experience

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  Fumate Co., Ltd.

  Jul 2004 - Feb 2007

  Research Engineer

  Job Description• Designing Electronic platform board for Xilinx FPGA, • Designing IP using Verilog, VHDL language.Project FPGA development board for education. (Xilinx virtex-E FPGA) VHDL IP for IEEE 802.11a (analog devices DAC/ADC, MAXIM RF module) VHDL IP for WCDMA Baseband modem testing (Digital IF up/down convertor, Digital FIR interpolation & Decimation filter) VHDL IP for IEEE802.15.3 High Data-rate WPAN system  (11,22,33,44, 55Mbps baseband modem, DQPSK/QPSK/16QAM/64QAM trellis coding)  VHDL IP & platform board for IEEE802.16 Cable MODEM. (DOCSIS_v3.0 uplink modem, flexible digital IF up/down converter, FIR filter) Show less

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  Mewtel Technology Co., Ltd.

  Feb 2007 - Apr 2011

  Associate Research Engineer

  Job Description• Designing electronic platform board for Xilinx FPGA, • Designing IP using Verilog, VHDL language.• Designing and Testing the Digital Wireless Communication systems.Project Testing/Simulation Bluetooth EDRv2.0 system (Verilog, MATLAB) Hardware platform board for IEEE.802.15.3a Multiband Ultra Wideband system. (Xilinx virtex5LX330, National semiconductor ADC08D1020, Fujitsu DAC MB86064, Samsung ARM CPU SC2440) Baseband Modem Verilog IP for IEEE.802.15.3a Multiband Ultra wideband system. (53.3Mbps-1024Mbps datarate, MB-OFDM, convolutional coding, viterbi decoder, reed-solomon codec, Dual-carrier Modulation (QPSK / 16QAM), Digital FIR filter) Show less

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  Advanced Digital Chips Inc.

  Apr 2011 - Nov 2014

  Senior Research Engineer

  Job Description• Designing SoC with EISC core CPU and digital wireless communication modem• Designing IP using Verilog, VHDL language.• Verification of various designed IPs on Xilinx FPGA.Project Integrate Top block and Power Management Unit (PMU) in Ultra Low Power Sensor Network (ULSN) system on 0.18um process SoC. MJPEG decoder for multimedia purpose CPU. 10/100 Ethernet MAC controller for Automotive SoC Technical Support for RN-171/131 WIFI module, microchips. Show less

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  HANCOM UNIMAX

  Jan 2015 - Jan 2020

  Job Description• Designing IP using Verilog, VHDL language.• Verification of various designed IPs on Xilinx FPGA.• DO-254, Requirement driven Verification• Managing Projects. Job Description• Designing IP using Verilog, VHDL language.• Verification of various designed IPs on Xilinx FPGA.• Managing Projects.Project Spacewire IP (on Actel FPGA board) DVI/ARINC818 video transceiver on 10GbE network system for Avionics (on Kintex7 FPGA and certifiable for DO-254)  MIL-STD-1553B IP customization (on Actel FPGA) FPGA verification and coverage analysis for DO-254 DAL-B in RDC(Remote Data Concentrator) Project

  • Principal Engineer

    Jan 2019 - Jan 2020

  • Senior Research Engineer

    Jan 2015 - Jan 2019
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  ED&C

  Jan 2020 - now

  Chief Engineer

  • Designing IP using Verilog, VHDL language.• Verification of various designed IPs by SystemVerilog.• DO-254, Requirement driven Verification consultant.• Technical supports for MentorGraphics EDA tools, QuestaSim.