Rahul Limaye

Experience

• 

  Intel Corporation

  Nov 1996 - now

  Maximize ASPs and profit through management of product SKUs, improve the efficiency and quality of the manufacturing process, define architecture for flawless execution and manufacturing. Develop business systems, tools, processes, and features for efficient time-to-market from concept through silicon manufacturing. IPs developed: Secure Digital, Thermal Sensor, Fuse, SRAMs, ROMs, RF, General Purpose IOs, Clocking, Band Gap, VRs, ADCs. New technologies: Integrated Embedded Controller (IEC) • Signaling specifications, timing budgeting and design parameters for the next generation memory• Leader of the execution team designing the transmitter, receiver, DLL, Vref, and Compensation.• Architect, memory AFEs • SOC and system clocking of Quark. • SOC and system clocking of IOTG, multi-purpose SOCs, and Wi-Fi designs• Clock and Reset Unit on Intel’s communication chip • Clock generation and distribution for inter-processor and memory IO links, and mega-cashes on Xeon and Itanium microprocessors. Special, functionality-rich clock library development on Itanium 2. Recipient of two Best Paper Awards in the internal conferences• Cache control and fuse blocks on 250nm and earlier technology products.

  • Architect and manufacturing expert, product configuration management

    Oct 2020 - now

  • Manager, Special Circuits Group, Client Chipsets

    Jan 2014 - Oct 2020

  • Panel Member, the 20th ACM/IEEE System Level Interconnect Prediction 2018

    Jun 2018 - Jun 2018

  • Team Lead

    Jan 1996 - Jan 2014

  • IP Lead, multi-level Memory Interface, Intel Corporation

    Jan 2012 - Jan 2013

  • IP Lead and SOC clock architect, Embedded and Communications Group

    Sept 2008 - Jan 2011

  • Technical Lead, Xeon, Itanium, and Pentium II with MMX® Technology Microprocessors

    Nov 1996 - Jan 2008