Nathan Erickson

Experience

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  UW Dept of Communications

  Jan 2001 - Jan 2003

  LAN Administrator

  Administered all aspects of IT for the department. Included responsibilities for purchase & setup of new computers and repair of old computers and LAN equipment on minimal budget, IT security, and interacting with people for tech support.

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  IBM

  May 2002 - Nov 2006

  ASIC Physical Design Engr

  IBM - International Business Machines Hardware Engineer 2003-11/2006Chip Physical Design - Layout, Placement Driven Synthesis (PDS), Route, & Timing of designs ranging from IP cores to large ASICs (10million+ gate) and Full Custom computer chips. Includes Clock Design, Placement Driven Synthesis, Design for Testability/Manufacturability.BlueGene supercomputer - Responsible for FPU core layout and design.Included Clock Design, Balanced Routing, bit stacking, PDS, semi-custom methodology, core rules generation, Methodology/DRC/LVS verification.Cell aka the PlayStation3 CPU - Responsible for RLM build and layout in a Full Custom methodology.Also worked on pervasive, scan (LSSD), and BIST functions.Aerospace and Defense - Worked on government projects that are ITAR restrictedIBM Hardware Engineer 2 Co-ops 2002 & 2003Working in GuardBand and Chip Physical Design departments at IBM Rochester. GuardBand - Stress testing systems and components to isolate and fix any problems.Chip Physical Design - Layout and timing correction of circuits for ASIC chips Show less

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  NTE Properties LLC

  Jan 2004 - Dec 2014

  Owner
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  LSI Logic

  Dec 2006 - Mar 2008

  Hardware Engineer

  Chip Physical Design - Floorplanning, Layout, Optimization, Clocking, Route, & Timing of cores for chips. Using Synopsis toolset and migrating from 90nm to 65nm with both tools and technology.

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  Texas Instruments

  Mar 2008 - Jan 2011

  Design Engineer

  Chip Physical Design - Floorplanning, Layout, Optimization, Route, & Timing of cores & chips. Working primarily on DSP and wireless baseband chips. Using advanced 40nm technologies.

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  Mentor Graphics

  Jan 2011 - May 2015

  Application Engineer

  Tool Expert in Olympus Place & Route with user support and design responsibilities. Help customers with all aspects of the chip and block Physical Design flow. Assist sale of existing and new tools in multi-million dollar accountsTraveling to work with clients in the US and EuropeWorking with multiple industry leading companies on critical projects.Creating, deploying, using, and teaching advanced design flow methodologies. Develop new techniques and functionality to handle new technologies and custom situations.Using leading edge process nodes including 40, 32, 28, and 20nm. Show less

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  Siemens EDA (Siemens Digital Industries Software)

  May 2015 - now

  FQA Engineer

  Developing and testing flows for Innovator 3D (formerly Xpedition Substrate Integrator), Die<->Package<->Board co-design and optimization tool. Enabling significant complexity and cost savings by intelligently planning the layout of multiple levels concurrently. Analysis, development, and automated testing for design flows.