Jen Sen Yang

Experience

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  Intel Corporation

  May 2002 - Jun 2012

  CPU design & validation Engineer

  Design automation engineer May 2002~Dec 2003Front end cluster design and validation engineer for pentium 4 Dec 2003~2004.Microcode validation engineer 2004Design architect for Core2solo 2005~2006Microcode design architect 2007~2010CPU Validation Architect for system validation 2011~2012

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  Altera

  Jun 2012 - Mar 2016

  Managing a team of 40 engineers delivering design flows & methodology for Altera’s next generation FPGA & SoC on leading edge process technology (20nm & 14nm). Perform research & analysis on various topics ranging from financial benchmarking of competitors, emerging FPGA markets, project retrospectives, Malaysia’s semiconductor landscape & ecosystem and organization health analysis.Assisting the VP of R&D in defining strategy, running operations & preparation of critical presentations.

  • Sr. Manager of Design Methodology & Solutions

    Nov 2013 - Mar 2016

  • Technical Assistant & Chief of Staff to VP of R&D Penang

    Jun 2012 - Oct 2013
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  Intel Corporation

  Apr 2016 - Feb 2024

  Leading the global Place & Route design, Layout Design and Design Methodology & Automation function for FPGA Hardware Engineering organization of PSG Intel. Responsible for the physical implementation of PSG's next generation FPGA product family on advance process nodes as well as developing the Methodology, Tools & Flows for RTL design, ASIC P&R design, Analog/Digital Circuit Design, custom layout design & infrastructure required for the development of FPGAs silicon. Managing the Place & Route design, Layout Design and Design Methodology & Automation function for the Hardware Engineering organization of PSG Intel in Penang. Team's responsibility includes delivery physical implementation for PSG's next generation FPGA product family on advance process nodes as well as developing the Methodology & Flows across RTL design, ASIC P&R design, Analog/Digital Circuit Design and custom layout design required for the development of FPGAs silicon.

  • Sr. Director of Physical Design, Methodology & Automation, Programmable Solutions Group

    Dec 2020 - Feb 2024

  • Director of Tiles, Design, Methodology & Automation, Programmable Solutions Group

    Apr 2016 - Nov 2020
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  Altera

  Feb 2024 - now

  Altera Silicon Design Engineering (SDE) Penang Site Lead & Sr. Director of PDLI

  Leading the Altera SDE in Penang.Leading the Altera SDE global DFT, Layout Design & Compute Infrastructure team. - Responsible for delivering the complete architecture to implementation DFT solutions & custom/analog layout designs for all Altera's FPGA products. - Responsible for the worldwide engineering compute infrastructure for Altera.