
Palash S

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About me
Staff Applications Engineer @ Synopsys India | IIT Indore
Education

Indian Institute of Technology, Indore
2018 - 2020Master's degree Communication and Signal processing
MIT Academy of Engineering, Alandi, Pune
2012 - 2016Bachelor's degree Electronics
Experience

NXP Semiconductors
Jun 2019 - Dec 2020Design Engineer
Jul 2020 - Dec 2020Student Technical Intern
Jun 2019 - Jun 2020

Marvell Technology
Feb 2021 - Aug 2023Senior Engineer
Synopsys Inc
Aug 2023 - nowStaff Application Engineer
Feb 2024 - nowSenior Field Application Engineer
Aug 2023 - Feb 2024
Licenses & Certifications

Genus Synthesis Solution
Cadence Design SystemsNov 2019
Physical Design Automation
Coursera
Low-Power Synthesis Flow with Genus Synthesis Solution
Cadence Design SystemsDec 2019
Conformal Equivalence Checking v19.1 (Online)
Cadence Design SystemsFeb 2021
Advanced Synthesis with Genus Synthesis Solution v16.2
Cadence Design SystemsDec 2019
Timing constraint Manager
Synopsys Inc
Prime time
Synopsys Inc
Clock tree synthesis
Udemy
Fundamentals of IEEE 1801 Low-Power Specification Format v5.0 (Online)
Cadence Design SystemsNov 2019
Basic Static Timing Analysis
Cadence Design SystemsDec 2019
Languages
- enEnglish
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