Vyom Garg

Experience

• 

  Central Institute of Educational Technology (CIET)

  Jun 2018 - Jul 2018

  Internship Trainee
• 

  Delhi Technological University (Formerly DCE)

  Mar 2019 - Jul 2021

  Research Assistant

  Student Researcher in VLSI Research design Group at Delhi Technological University Worked on OTRA based devices, shadow filters, CMOS implementation inductors.

• 

  Defence Research and Development Organisation (DRDO)

  Jun 2019 - Jul 2019

  Summer Internship

  Trainee in the IR waves analysis division Studied AC Response of Passive and Active Low Pass Filters and Performed Monte Carlo and noise analysis on Pspice A/D to determine which filter provides an optimal solution as per requirement at SSPL.

• 

  Summer Research Fellowship Program 2020

  May 2020 - Jul 2020

  Summer Research Fellow

  Selected as a summer research fellow under guidance of Dr, Manoj Saxena, Delhi University and simulated the Total Ionisation Dose effects and single event upset effects on various MOSFET and line TFET using Silvaco TCAD.

• 

  Ansys

  Jan 2021 - now

  Fast-track promotion, 1 Year ahead of track. • Engaged in Infrastructure Development, Spec Design, and Validation for Redhawk – SC.• Collaborated on a pre-silicon solution for identifying vulnerabilities of Crypto Systems when subjected to Side Channel or Fault Injection Attacks at various design abstraction levels.

  • Senior Product Specialist

    Apr 2024 - now

  • Product Specialist II

    Apr 2023 - Mar 2024

  • Product Specialist

    Jul 2021 - Apr 2023

  • Intern

    Jan 2021 - Jul 2021