Jan Ludvik

Experience

• 

  CEDO s.r.o.

  Sept 2002 - Mar 2010

  An external senior back-end designer for Virage Logic company.Responsibilities: B.E. views (schematic and layout) of standard cell libraries, simulations and characterization of basic CMOS blocks, scripting in PERL, Bash and Cadence SKILL languages, 3rd level support expert. An external senior back-end designer for NXP company.Responsibilities: B.E. views (schematic and layout) of standard cell libraries, simulations and characterization of basic CMOS blocks, scripting in PERL, Bash and Cadence SKILL languages, 3rd level support expert. An external senior back-end designer for Philips Semiconductors company.Responsibilities: B.E. views (schematic and layout) of standard cell libraries, simulations and characterization of basic CMOS blocks.

  • Microelectronic B.E. Senior Designer

    Oct 2009 - Mar 2010

  • Microelectronic B.E. Senior Designer

    Jan 2006 - Oct 2009

  • Microelectronic B.E. Designer

    Sept 2002 - Jan 2006
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  ON Semiconductor

  Jul 2010 - Jul 2023

  IP Development Engineer - Senior Physical Design Engineer

  A physical design (B.E.) engineer responsible for a RAM/ROM testing chip implementation (P&R), a physical verification expert and IP audit methodology consultant.Details:- Place and route flow and methodology of digital/mixed test chips, floor-planing timing closure, STA, clock tree synthesis, power distribution mesh and flow customization in Encounter Digital Implementation tool.- Design of standard cells and custom digital blocks in Cadence Virtuoso DFII- Methodology of standard cell libraries - GDSII, LEF and CDL and parasitic netlist views- Experienced with 28 nm up to 500 nm nodes, some knowledge about 22 nm and smaller- Scripting in TCL, BASH, SKILL and PERL- Physical verification in MGC Calibre (DRC,LVS) or Cadence PVS- Mixed signal simulation in HSpice, Spectre or ELDO, - Parasitic extraction in Calibre or QRC- Technical and project documentation Show less

• 

  ASICentrum spol. s r.o.

  Aug 2023 - now

  Senior Physical Design Engineer