Qingming Zhou

Qingming Zhou

Hardware engineer

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location of Qingming ZhouMinhang District, Shanghai, China

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  • Timeline

  • About me

    Hesai Technology - Senior Hardware Design Engineer

  • Education

    • 哈尔滨工业大学

      1996 - 2000
      学士 电气工程
    • 哈尔滨工业大学

      2000 - 2003
      硕士 电气工程
  • Experience

    • Maipu Communication Technology Co.,Ltd

      Jul 2003 - Dec 2004
      Hardware engineer

      Designed the advanced Ethernet switch based on MPC8245. Develop and implement line card scheme with Capture and PCB layout, Responsible for the time analysis of DDR/SDR interface and research for high speed design.

    • 中兴

      Dec 2004 - Aug 2006
      Senior hardware engineer

      TD-SCDMA base station, Responsible for digital IF board, including digital up-converter(DUC)、digital down-converter(DDC)、high frequency A/D、D/A、PLL、VCO and clock circuit. Research for digital IF solution based on TMS320C6482 applied in TD-SCDMA.

    • Avonaco Systems Inc

      Aug 2006 - May 2009
      System engineer

      作为硬件部门负责人,负责媒体服务器产品(一款3G核心网产品)的硬件架构设计、总体方案设计、关键器件选型、整个设备的原理图设计、PCB设计,从产品定型、设计、调试、测试、发货,全程负责。该产品为一个基于ATCA标准的密集DSP集群平台,硬件架构为data/control plane的DSP集群和manage plane的ARM集群,主要技术标准为ATCA/uTCA、AMC,主要互连技术为GE、RapdIO,核心芯片为Cavium 4核网络处理器OCTEON CN5830和Freescale 4核DSP MSC8144、MSC8122。其他主要芯片包括98DX240/88E1149/LPC2468等,主要并行接口为72bit SODIMM。该产品包含4块板卡,一版定型成功率为50%。

    • Alcatel-Lucent Shanghai Bell

      May 2009 - Mar 2018

      Experience position: 5G BBU system engineerJob description: responsible for hardware development of 5G baseband fronthaul switch (FHS) board, design hardware structure; choose the key chips, write HW implementation document, design schematic and guide PCB design, write HW test case, hardware debug and prototype test. Key chips include high performance FPGA which implement CPRI/Ethernet transmission and 10GE switch/PHY. Main parallel interface is DDR4-2400.Experience position: 4G BBU system engineerJob description: responsible for hardware development of 4G baseband unit(BBU) acceleration engine(BAE) card. responsibility: design hardware structure; choose the key chips, write HW implementation document, design schematic and guide PCB design, hardware debug and prototype test. Key chips include multi-core SoC embedded with DSP cores(StarCore) and PowerPC cores(e6500). Main parallel interface is DDR3-1600. Show less

      • HW system engneer

        Feb 2014 - Mar 2018
      • HW system engineer

        May 2009 - Jan 2014
    • Hesai Technology

      Apr 2018 - now
      Lidar Senior Hardware Design Engineer
  • Licenses & Certifications

    • PMP