Anuj Patel

Experience

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  Samsung Electronics

  Jul 2005 - Apr 2011

  • Led Product QRE responsible for ensuring outgoing quality and reliability of DRAM and NAND FLASH products, through statistical methodologies to automate the control of outgoing product quality.• Performed Accelerated product tests (Endurance, GBB, HTS/HTDR, Extended Burn-In) for evaluation of critical process changes or out-of-spec abnormalities.• Led several cross-functional company wide projects to implement systems for improved early detection of potential quality and reliability concerns.• Led excursion management activities, which involved coordinating with the multiple departments to contain the at-risk material, characterizing device parametric performance through extended reliability testing, and developing a disposition plan for abnormal material handling. Show less

  • Product Quality and Reliability Engineer

    Jul 2006 - Apr 2011

  • Manufacturing Quality Engineer

    Jul 2005 - Jul 2006
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  SAMSUNG FOUNDRY

  Apr 2011 - Mar 2018

  • Technical lead for FEOL and MOL reliability, owning all activities from early stage process qualification and technology transfer through manufacturing ramp-up across multiple technology nodes (14/20/28/32/45nm) and products (SoC, ASIC, DDI).• Successfully achieved HVM (high volume manufacturing) line transfer qualification for Samsung 14nm FINFET and 20nm Planar technologies. Owned all FEOL device reliability issues related to transistor aging (HCI, BTI) and gate oxide breakdown (TDDB, V-ramp), and supported reliability evaluations to enable continual process improvements for aggressive yield-up targets.• Responsible for pre-qualification product/process margin analysis with respect to customer HTOL stress conditions, and early stage process optimization to mitigate HTOL failure risk, thereby enabling faster qualification cycle and ramp-up.• In-charge of extrinsic reliability risk management post qualification with specific focus on collaborating with the Process Integration team for yield enhancement to reduced defect limited failures, and with Product Test team to establish accelerated tests (DVS, EVS) to provide adequate test screen.• Hands-on experience with reliability test, device characterization, and extraction of reliability model parameters.• Led the successful setup of the first Wafer Level reliability lab at Samsung’s Austin facility. This includes procuring test equipment, developing test methodology and algorithms, and establishing necessary business processes for operation. Show less

  • Senior Process Integration Engineer

    Nov 2017 - Mar 2018

  • Senior Reliability Engineer, Technical Lead

    Apr 2011 - Nov 2017
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  Cirrus Logic

  Apr 2018 - Jul 2022

  Sr Staff Reliability Engineer

  • Owned new product reliability risk assessment and qualification plan from the initial concept phase through mass production.• Worked with product engineering teams to drive successful execution of Product (HTOL/LTOL, ELFR, ESD/LU) and Package (HTS, HAST, TC) qualification stresses, and lead root cause resolution activities in case of failures.• Board Level Reliability program manager and lead responsible for all qualification activities, including test vehicle definition, reliability stress planning, logistics, execution, and technical data analysis.• Collaborated with Silicon and Package Technology teams to evaluate reliability of new technologies with particular focus on company specific IP.• Provide reliability modeling support to Design teams for early-stage risk assessment.• Worked with internal and external technical groups to develop new capability and reliability methodologies.• Supported the customer quality engineering team to engage customers and ensure that the reliability and quality of the product meets both internal and external standards. Show less

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  AMD

  Aug 2022 - now

  PMTS Product Development Engineer