Kyota WATANABE

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Fujisawa, Kanagawa, Japan

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Timeline
About me
Memory Design Engineer, Ph.D.
Education
- Tohoku University
  2010 - 2014
  Bachelor of Engineering - BE Information and Intelligent Systems
- Tohoku University
  2015 - 2019
  Doctor of Philosophy - PhD Electronic Engineering
- Tohoku University
  2014 - 2015
  Master of Engineering - MEng Electronic Engineering
Experience
- Tohoku University
  Apr 2015 - Mar 2019
  - Research Institute of Electrical Communication, Tohoku University- Research on spintronics memory technologies - materials and device engineering for ultrasmall magnetic tunnel junctions. Advisers: Prof. Hideo OHNO / Prof. Shunsuke FUKAMI
  - JSPS Research Fellow (DC2)
    Apr 2017 - Mar 2019
  - Graduate Program on Spintronics (GP-Spin)
    Apr 2015 - Mar 2019
- SPINTEC
  Jan 2018 - Jun 2018
  Student Internship
- JAXA: Japan Aerospace Exploration Agency
  Apr 2019 - Jun 2022
  Research Engineer
- TSMC Design Technology Japan, Inc.
  Jul 2022 - now
  Senior Engineer
Licenses & Certifications
- Programming Foundations: Fundamentals
  LinkedIn
  Aug 2024
  View certificate
- Data Visualization in Python with Dash
  LinkedIn
  Jul 2024
  View certificate
Volunteer Experience
- Technical support in the 3rd UN World Conference on Disaster Risk Reduction
  Issued by Tohoku University on Feb 2015
  Associated with Kyota WATANABE