Mark Firstenberg

Experience

• 

  Digital Equipment Corporation

  Jun 1981 - Oct 1994

  Defined and specified a C++ based RTL hardware description language.• Developed an RTL compiler to improve RTL simulation performance.• Investigated logic simulation performance improvements, including specifying a high performance event driven simulation kernel.• Demonstrated potential parallel processing performance enhancements for cycle-based simulation, and phase partitioning/node ordering of RTL representations.• Wrote specifications for and gave seminars on the above topics. Show less Responsible for the design, implementation and verification of firmware and hardware (ECL gate arrays) for the last stage of the VAX 9000 CPU’s prefetching, pipelined IBOX. This pipeline stage evaluates VAX operand specifiers and either issues memory requests on behalf of or delivers immediate data directly to the CPU’s execution units.Received four patents related to VAX 9000 CPU design.Proposed, designed and implemented a network compiler which produces a VAX based gate level simulation capable of execution speeds equal to or greater than equivalent models implemented using DECSIM behavioral software and ZYCAD hardware accelerators. Using this cycle-based simulation technique, the VAX 9000 system design team was able to simulate over 30 billion CPU cycles (approximately 8 minutes of real VAX 9000 CPU time) before hardware prototype fabrication. Show less

  • Principal Software Engineer

    Apr 1991 - Oct 1994

  • Principal Hardware Engineer

    Mar 1985 - Mar 1991

  • Hardware Engineer II

    Sept 1982 - Apr 1985

  • Hardware Engineer II

    Jun 1981 - Aug 1982
• 

  Viewlogic Systems, Inc.

  Nov 1994 - Jan 1996

  Principal Software Engineer

  Investigated aspects of Hardware/Software Co-design and prototyped a low cost Hardware Modeler. Researched analysis aspects of High Performance PCB design.

• 

  Stratus Computer, Inc.

  Feb 1996 - Feb 1998

  Principal Software Engineer

  Supported Design Verification tools, with an emphasis on improving Verilog RTL simulation performance. Supported tools included:Verilog simulators: Verilog-XL, VCS and Speedsim/3Test Bench Development: SpecmanFormal Verification: Design Verifier, Design Insight and FormalCheckMiscellaneous: Clearcase, SignalScan and VeriCov

• 

  Sun Microsystems

  Mar 1998 - Jun 2004

  Senior Staff Engineer

  Evangelized and implemented the UltraSPARC V RTL methodology, including:• Defining RTL coding rules and version release policies,• Developing and supporting the RTL primitive library in support of all RTL customers, including functional simulation (both software and hardware acceleration), implementation and DFT,• Implementing the functional simulation model build and RTL rule enforcement procedures,• Defining RTL assertion methodology, enabling assertion based verification and formal model checking,• Co-authoring the RTL to schematic comparison methodology,• Forming and leading a company-wide group to promote cycle-based simulation and other simulation performance improvement methods, and• Mentoring engineers informally within the UltraSPARC V group and formally within the Sun Engineering Enrichment and Development program.Originated the SPARC Instruction Set Simulator, which was used as the reference model for RTL verification and enabled stand-alone test verification environments.Wrote the first SPARC Assembler (including verification specific extensions) used on the UltraSPARC V project.Proposed a design for implementing a pseudo random code generator capable of creating complex control structure and multi-threaded tests. Show less

• 

  IBM

  Jul 2004 - Jul 2013

  Senior Technical Staff Member

  Considered IBM’s sequential equivalence checking methodology expert:• Implemented and deployed sequential equivalence checking flows (using SixthSense, an IBM internal tool) for 10 processor projects including XBOX 360 SOC cost reduction, embedded FPU cycle time improvement, Verilog to VHDL translations and Power7 to Power7+ technology transfer.• Trained designers and supported their use of these tools and methodsDeveloped 6 intricate VHDL formal verification test benches for Power7, Power8 and Z processor designs. Specifically, formal verification of:• 64 bit/64 byte ECC (Power7),• Inter-processor bus operations and latency (Power8), and• Register renaming PSW (Processor Status Word) logic for a threaded out of order execution processor (Z). Show less

• 

  Jasper Design Automation

  Sept 2013 - Jun 2014

  Sr. Staff Applications Engineer

  Formal verification methodology and support, concentrating on sequential equivalence checking.

• 

  Intel Corporation

  Nov 2014 - Feb 2017

  Staff Engineer

  Support Front End Tools/Flows/Methodologies for a government project.

• 

  AMD

  Mar 2017 - now

  Principal Member Of Technical Staff

  Sequential equivalence checking and formal methods