Jayasekhar Tholiyil

Experience

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  ISRO - Indian Space Research Organization

  Jan 1994 - Jan 2000

  Digital Design Engineer

  Logic Design targeted towards various telemetry systems. Design implementation targeted towards FPGA

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  BRI Incorporated

  Jan 2000 - Jan 2002

  Design Engineer

  Logic Design and development of IPs for various network processor platforms. Peripheral controller logic implementation.Signal Integrity and Static Timing Analysis of platform Designs.

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  Intel Corporation

  Jan 2002 - now

  Senior SOC micro Arch & Design Engineer

  Versatile SoC Architecture, Micro-Architecture, Design, Debug and end to end ownership.* SoC Architecture of fabrics across various bus protocols, CPU subsystems, and SoC peripherals. * Micro-Architecture, Configurable RTL Development and ownership of the Design from concept through production. * Design development includes ARM-based SoC and fabrics, PCI-based interconnect fabric and End Points* Management units for Server chipsets, BIST engine for PCIe.* Owned Design development from concept through production.* SD support, Timing closure, various pre tape-in quality reviews.* Technical leadership demonstrated through debug expertise, fabric content expertise and mentorship. Show less