SEBIN PUTHIYATH

SEBIN PUTHIYATH

ASIC Physical Design Trainee

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  • Timeline

  • About me

    Physical Design Engineer

  • Education

    • Carmel Polytechnic College, Alappuzha

      2011 - 2014
      Diploma in Engineering Electrical, Electronics and Communications Engineering 8.4 CGPA
    • Cochin University of Science and Technology

      2014 - 2018
      Bachelor of Technology - BTech Electronics and Communications Engineering 7 CGPA
    • Vellore Institute of Technology

      2020 - 2022
      Master's degree VLSI Design 7.3 CGPA
  • Experience

    • RV-VLSI VLSI and Embedded Systems Design Center

      Nov 2018 - May 2019
      ASIC Physical Design Trainee

      Implementation of Lakshya Block-level design at 40nm Technology node from Floorplan to Sign-off comprising of 34 macros and 38921 Standard cells With 7 levels of metal layers and clock frequency at 833 Mhz. multimode multi-corner analysis was performed on the design using 600mW power consumption in the 4.2 mm.sq. area using Synopsys ICC2 and Primetime.

    • Netrasemi Private Limited

      Oct 2021 - Jun 2022
      Physical Design Intern

      Low power structural design of Cortex M33 based ARM SoC subsytemCadence EDA used: Xcelium, Genus, Innovus, Tempus

    • HCLTech

      Jun 2022 - now
      Member Technical Staff

      PD Flow:Floorplanning, Power Planning, Clock Tree Synthesis, Routing, Custom Routing, Timing Analysis.Tools Used: Synopsys-Fusion Compiler, ICC2, Formality, PrimeTime, ClockBuilder; Cadence-Innovus, Tempus

  • Licenses & Certifications

    • Digital Physical Design Domain Certification

      Cadence
      Jun 2025
      View certificate certificate
    • Innovus Implementation System (Block) v21.1 Exam

      Cadence Design Systems
      Nov 2022
      View certificate certificate
    • Semiconductor 101 v1.0 Exam

      Cadence Design Systems
      Aug 2024
      View certificate certificate
    • Basic Static Timing Analysis v2.0 Exam

      Cadence Design Systems
      Oct 2022
      View certificate certificate
    • Voltus Power Grid Analysis and Signoff with Stylus Common UI v21.1 Exam

      Cadence Design Systems
      Oct 2022
      View certificate certificate
    • Cadence RTL-to-GDSII Flow v5.0 Exam

      Cadence Design Systems
      Jun 2023
      View certificate certificate
    • VSD Intern - Mixed Signal Physical Design Flow with Sky130

      Udemy
      May 2022
      View certificate certificate
    • Voltus Power Grid Analysis and Signoff v20.1 Exam

      Cadence Design Systems
      Apr 2022
      View certificate certificate
    • Cadence RTL-to-GDSII Flow v3.0 Exam

      Cadence Design Systems
      Jul 2022
      View certificate certificate
    • Advanced Diploma in ASIC Design

      RV-VLSI VLSI and Embedded Systems Design Center
      Jun 2019