SEBIN PUTHIYATH

Experience

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  RV-VLSI VLSI and Embedded Systems Design Center

  Nov 2018 - May 2019

  ASIC Physical Design Trainee

  Implementation of Lakshya Block-level design at 40nm Technology node from Floorplan to Sign-off comprising of 34 macros and 38921 Standard cells With 7 levels of metal layers and clock frequency at 833 Mhz. multimode multi-corner analysis was performed on the design using 600mW power consumption in the 4.2 mm.sq. area using Synopsys ICC2 and Primetime.

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  Netrasemi Private Limited

  Oct 2021 - Jun 2022

  Physical Design Intern

  Low power structural design of Cortex M33 based ARM SoC subsytemCadence EDA used: Xcelium, Genus, Innovus, Tempus

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  HCLTech

  Jun 2022 - now

  Member Technical Staff

  PD Flow:Floorplanning, Power Planning, Clock Tree Synthesis, Routing, Custom Routing, Timing Analysis.Tools Used: Synopsys-Fusion Compiler, ICC2, Formality, PrimeTime, ClockBuilder; Cadence-Innovus, Tempus