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Harshala Patil

Harshala patil

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location of Harshala PatilAustin, Texas, United States
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Followers of Harshala Patil3000 followers

  • Timeline

  • About me

    Senior Quality & Reliability Engineer at Samsung Semiconductor

  • Education

    • University of mumbai

      2009 - 2013
      Bachelor of engineering (b.e.) electronics and telecommunications engineering

    • Rochester institute of technology

      2013 - 2015
      Master of science (m.s.) electrical and microelectronic engineering

  • Experience

    • Rochester institute of technology

      Jan 2015 - May 2015
      Teaching assistant

      • Assisted Dr. Lynn Fuller [Professor, Emeritus, Electrical-Microelectronic Engineering and IEEE Life Fellow] in teaching graduate & undergraduate microelectronic courses and lab work.• Graded assignments for ~50 students and provided tutoring for classroom/lab queries.

    • Globalfoundries

      May 2015 - Feb 2019

      • Led process flow experiments in FEOL & MOL on both TD (Technology Development) and HVM (High Volume Manufacturing) to enhance process margin and yield.• Owned critical layers in wafer fabrication process like multi-patterning tone inversion self-aligned contact trench silicide, gate contact, via interconnects, gate module, alternate metallization schemes etc.• Collaborated with Pathfinding team to develop Process Design Kit components for technology performance analysis.• Owned process matching technical spec scorecard and led fab-wide 300mm silicon substrate process qualification across multiple vendors.• Led Region E bevel defect improvement project, resulting in enhanced product quality and yield.• Championed EUV process flow and other path to profitability projects, driving innovation and cost-efficiency. Show less

      • 7nm & 14nm Senior Process Integration Engineer (TD/HVM)

        Feb 2017 - Feb 2019

      • 10nm and 7nm Characterization Engineer

        Feb 2016 - Feb 2017

      • 28nm and 14nm Process Integration Co-Op Engineer

        May 2015 - Feb 2016

    • Micron technology

      Mar 2019 - Sept 2021
      Process integration engineer (tech transfer)

      • Led the transfer of 3DxP and next-gen memory tech from Micron’s R&D fab to Utah manufacturing facility.• Developed alternate integration schemes, collaborated with process teams for NPI (New Product Introduction), and communicated project plans to senior leadership.• Conducted feasibility studies for integrated process solutions, focusing on safety, quality, and yield output requirements for transfer to HVM.• Specialized in Design of Experiment (DOE) for low yield analysis and tool chamber commonality check.• Led Task Force Teams to enable solutions and improve KPI's for product performance, minimizing scrap, cycle time reduction, and reticle qualification.• Implemented Q-Time/N2 bin purge setup to enhance operational efficiency and drive continuous improvement. Show less

    • Samsung semiconductor

      Sept 2021 - now
      Senior quality & reliability engineer

  • Licenses & Certifications

    • Supply chain management

      Rutgers university
      May 2021

    • Six sigma green belt

      University system of georgia
      Mar 2021

    • Aiag iatf 16949 lead auditor and supplier auditor certification

      Aiag - automotive industry action group

    • Project management specialization

      University of california, irvine division of continuing education
      May 2020

  • Honors & Awards

    • Awarded to Harshala Patil
      IEEE Senior Member IEEE IEEE Senior Membership is an honor bestowed only to those who have made significant contributions to the profession. Only 10% of IEEE’s more than 450,000 members hold this grade, which requires extensive experience, and reflects professional maturity and documented achievements of significance.