Deep Enrich
Mir tanveer islam
728 followersTimeline
About me
RTL design | Verilog | FPGA | VLSI | Digital Design
Education
College of development alternative
2006 - 2007Secondary school certificate science 5.00
North south university
2010 - 2015Bachelor of science (bs) electrical and electronics engineering 3.11Activities and Societies: Society of Science Engineering and Technology (NSU-SSET) Electrical and Electronics Engineering
Drmc - dhaka residential model college
2008 - 2009Higher secondary school certificate science 4.10Activities and Societies: Remains Debating Society (RDS)
California state university, fullerton
2022 - 2024Master of science - ms electrical engineering 4.0
Experience
Adn technologies ltd.
Nov 2017 - Aug 2018Assistant engineer
Neural semiconductor limited
Sept 2018 - Oct 2021Design engineer (rtl/fpga)Design & Develop RTL modules for ASIC and FPGA to meet all requirements.Implement and validate designs on FPGA platforms, ensuring accuracy and reliability
California state university, fullerton
Feb 2023 - May 2024Graduate Teaching Assistant
Aug 2022 - May 2024Graduate Research Assistant
Feb 2023 - Dec 2023
Licenses & Certifications
- View certificate
Verilog language and application v27.0
CadenceFeb 2025
- View certificate
Design for test fundamentals v5.0
CadenceSept 2024 - View certificate
Using altera® quartus® prime software
Intel corporationFeb 2025 - View certificate
Jasper app for early design verification v24.03
CadenceDec 2024
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