Ramesh Kandula

Experience

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  STMicroelectronics

  Jun 1999 - Jun 2001

  EDA Software Engineer

  Worked on developing software for FPGA Software Tool, contributed to Static Timing Analyzer tool development.

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  QuickLogic Corporation

  Jun 2001 - Aug 2004

  Senior EDA Software Engineer

  Worked on enhancing QuickLogic Static Timing Analyzer module supporting various new features and reporting models for the new products, like QuickMIPS, SerDes, etc.

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  Infineon Technologies

  Aug 2004 - Mar 2006

  Senior EDA Engineer

  Worked on developing a new Timing Signoff methodology engine called OTALAB to compare the Timing Analysis results between tools PrimeTime (Synopsys) and BlastFuision (Magma).

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  Conexant

  Apr 2006 - Aug 2011

  Principal EDA Engineer

  Responsible for EDA Tool Bench-marking, Global Licensing and Administration.Also contributed to Design Flow Automation on Timing Closure.Worked as Senior Engineer from Apr to Sep 2006 in Design Verification group, at Skyworks Solutions, Hyderabad, before Conexant Systems bought our group.

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  Broadcom

  Sept 2011 - Mar 2019

  Principal EDA Engineer

  Responsible for Global EDA Tool and Licensing Administration, Bench-marking and Automation Projects.Worked as Consultant for EDA Tools and License Administration at Broadcom from Sep 2011 till Dec 2013 before absorbed as Principal Engineer

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  Micron Technology

  Apr 2019 - Oct 2021

  Principal Engineer

  Benchmarking on EDA Tools performance and EDA Tool Administration.

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  Silicon Labs

  Apr 2022 - now

  Staff Engineer