Gior Goh

Experience

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  Keysight Technologies

  Feb 2020 - Jan 2020

  Firmware Engineer
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  SkyeChip

  Nov 2022 - Jan 2023

  Design Verification Engineer

  The main jobscope is to handle the Test chips IPs by writing UVM testbench to validate the functionality of the design. Another support provided is validate software models from frontend by testing the GUIs of the software and validate the functionality of the backend through the help of a software framework by python script.Involved in Software QA team by validating chi command transactions through the use of python scripts to automate the process flow. Filed Jira tickets to report the issues that is generated from the ticket to make correct the software binary files generated.Wrote system Verilog assertions on some RTL designs to check for the conditions of RAMInvolved in writing UVM tests for validating design under test (DUT) through the sequences generated from the UVM testbench. Assisted in coverage tracking and provide feedback on how to improve the coverage for the project DUT.Ensure that the tests written fulfilled the requirements by viewing through the Synopses DVE tools and checking the waveform and the test logs generated from the tests. Tunjukkan kurang

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  AdoreSys Pte Ltd

  Jan 2024 - now

  Design Verification Engineer