Talk to sales Try for Free
Charles Chou

Charles Chou

Internship Trainee

location of Charles ChouHsinchu Metropolitan Area

Connect with Charles Chou to Send Message

Connect

Connect with Charles Chou to Send Message

Connect

  • Timeline

  • About me

    Memory Design Engineer

  • Education

    • 國立臺灣科技大學

      2015 - 2017
      Master's degree Department of Electronic and Computer Engineering (Electronic System) GPA: 3.97/4.0

      » Specializing in Analog IC Design and Power Management IC Design.» Masters Dissertation: A DC-DC Boost Converter with Adaptive On-Time Control and Zero-Current Switching for Energy Harvesting System. (Supervised by Prof. Poki Chen)

    • 明志科技大學

      2011 - 2015
      Bachelor's degree Department of Electronic Engineering Grade Ranking No. 1 in the Department of Electronic Engineering (1/103)

      Directed Individual Study: Analog IC Design, including Integrated Analog Filters Design. (Supervised by Prof. Hua-Pin Chen)

  • Experience

    • 緯創資通

      Sept 2013 - Sept 2014
      Internship Trainee

      【Product Development Div., Server BU】» Server Hardware Technique Support for HP- To Perform Failure Analysis & RMA for Products. - Products Function Verification & Measurement Support for R&D. - Rework Support for R&D.

    • Elite Semiconductor Microelectronics Technology Inc

      Dec 2017 - now
      Senior Principal Engineer

      【Flash Design Dept., Memory BU】» Responsibility: Design of READ Sensing Critical Path for All NOR Flash Products- READ Timing Control Design.- Sense Amplifier Design.- The Consideration of Sensing Data Bus Critical Path. - READ Functional Verification. - Output Buffer Design including Pre-driver, OCD, etc.- HV Circuit Path Design including LDO.- Layout Floor Planning and Review for READ Sensing Critical Path.- Debugging for READ-related Products Issues.» Experience of SPI NOR Flash Products Design:- Fabrication Technology: 90nm, 65nm, 50nm, and 48nm - Memory Density: 4Mb, 8Mb, 16Mb, 32Mb, 64Mb, 128Mb, 256Mb, and 512Mb- Operating Voltage: 3.3V, 1.8V, and Wide Voltage (1.65-3.6V)Range Show less

  • Licenses & Certifications

    • Certificate of Completion: Energy-saving Power Management Integrated Chip Design (learned in a 12-hour training course)

      Tze-Chiang Foundation of Science and Technology
      Nov 2019

    • Certificate of IC Layout Design Capability Identification

      National Chip Implementation Center, CIC
      Jul 2015

    • Certificate of Advance Printed Circuit Board Layout and Design, Engineer Level

      Taiwan Innovation Technology Management Development Association
      May 2013

    • Technician Certificate of Computer Maintenance, class C skill category

      Council of Labor Affairs, Executive Yuan, Republic of China
      Jul 2010

  • Honors & Awards

    • Awarded to Charles Chou
      Internship Excellence Award Ming Chi University of Technology Sep 2014 Job Recommendation from Internship Recruiter - Wistron Corporation.