Sharada Mohan

Experience

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  AMD

  Jan 2010 - Oct 2011

  Worked on design verification infrastructure - debugged complex verification environment issues. Automated flows.Developed tools to support complex compilation flow.Worked on various regression and testlist management tools.x86 test case debug.

  • Design Engineer

    Jul 2010 - Oct 2011

  • Design Engineer

    Jan 2010 - Jan 2011
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  Arm

  Oct 2011 - Oct 2019

  System Validation - Understanding of System Architecture & memory map.Integration of ARM IPs into our SOC.Integration testing. Exposure to simulation & emulation (both PXP & veloce) verification environments.Memory controller validation - Stress testing of ARM's Enterprise class memory controller. Understanding of DDR2, DDR3, DDR4 protocol.DRAM Memory subsystem debug. ARM assembly programming.Kits and subsystems - -Delivered a number of "kits" which are highly configurable SOCs comprised of ARM IPs - verified with system level test cases. -This involved the use, enhancements and many modifications to the underlying auto stitching integration framework. Development of the test bench specification required for ARM mobile Subsystem verification. Owned the entire planning, development and maintenance of the test bench for ARM mobile subsystem.System validation of ARM V8R class CPUs - -Involved in the complete integration, bring up and verification of the V8R platform on both emulation and simulation, right from development of System level test plan and test scenarios through out the development cycle of the CPU IP. System level validation of ARM enterprise class interconnect which involves planning, implementation andexecution of stress test cases scenarios to find RTL bugsEvaluation and bring up of CHI AVIP from Cadence - integrated into our system environment.Enhancement and verification of an in-house AMBA CHI traffic injector VIP on Veloce Strato emulator - deployed both of these CHI traffic injectors for use across the team to be used as a replacement for large design CPUs targetting interconnect stress verification. Tech lead for the overall system level verification of the latest Aarch64 V8R class CPUtargeted for the mobile modem, HDD, SSD and automotive ADAS markets Show less

  • Senior Verification Engineer

    Jan 2015 - Oct 2019

  • Verification Engineer

    Oct 2011 - Dec 2014
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  Infineon Technologies

  Nov 2019 - Aug 2022

  Business Partner
• 

  UST

  Nov 2019 - Aug 2022

  Engineering Lead

  I worked as a Business Partner with the client Infineon, Singapore

• 

  Arm

  Aug 2022 - now

  Leading Client Solutions For Kits and managing a team that delivers SoC like systems to internal stakeholders involving Client IPs such as interconnects, compression technology & SMMU

  • Principal Engineer

    Apr 2024 - now

  • Staff Engineer

    Aug 2022 - Apr 2024