Experience

• 

  Huawei

  Dec 2018 - Mar 2019

  Core network engineer
• 

  Accenture

  Jun 2019 - Oct 2019

  Associate software engineer
• 

  Fiberhome

  Jan 2020 - Mar 2020

  Osp design engineer
• 

  Rohm lsi design philippines, inc.

  May 2022 - now

  We write Verilog RTL codes to create test pattern and design a circuit, run RTL and gate simulation to verify the function of different products if it is align with its specifications, checking code coverage and create documentation.

  • Assistant Logic Integration Engineer

    Oct 2024 - now

  • RTL Engineer

    Feb 2023 - Oct 2024

  • RTL Engineer Trainee

    May 2022 - Feb 2023