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Ghanshyam Verma

Ghanshyam Verma

Intern

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location of Ghanshyam VermaRaipur, Chhattisgarh, India

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  • Timeline

  • About me

    RTL Design Engineer @ XDLINX Lab || FPGA Engineer in CR RAO AIMSCS || M.Tech. in IIIT-Naya Raipur

  • Education

    • Chhattisgarh Swami Vivekanand Technical University (CSVTU)

      2015 - 2019
      Bachelor of Engineering - BE Electrical and Electronics Engineering 75%

    • IIIT-Naya Raipur

      2021 - 2023
      Master's degree VLSI & EMBEDDED SYSTEMS 8.59

  • Experience

    • Aviatech Enterprises Private Limited

      Apr 2023 - May 2023
      Intern

      Repair/servicing of Avionics/ Test Equipment/ ATEs repairs pertaining to our major service providers. Indigenization of electrical and avionics items/ PCBs for more information and much more.

    • CR RAO AIMSCS

      Jun 2023 - Apr 2024
      FPGA Engineer

      Designing and optimizing individual modules, such as NTT, Inverse NTT, Montogomery, Compression, Encode, Decode etc. for better performance of CRYSTAL Kyber KEM.KEY exchange mechanism performed in Server-Cleint in two FPGA Board.Integration of RTL Blocks like KeyGen, Encryption, Decryption Modules and Hardware Debug, Validation, Post-Synthesis.

    • XDLINX Labs

      Apr 2024 - now
      FPGA RTL Design Engineer

      Working on integration various sub modules of an in-house designed SDR and also verifying theintegrated blocks by collecting the end-point data through the above developed AXI DMA Interface.Worked on developing an AXI DMA interface to facilitate data transfer from PL logic to PC through PSand TCP/IP Ethernet protocol

  • Licenses & Certifications

    • Mixed Signal Circuit Design and Simulation Hackathon certificate using e-Sim. organized by IIT Bombay.

      FOSSEE IIT Bombay

    • Cloud Based Analog IC Design Hackathon Certificate as an initiative of IIT Hyderabad.

      As an initiative of IIT Hyderabad, which has been sponsored by Synopsys.

    • IEEE certificate for serving as a Volunteer

      IIIT-Naya Raipur