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Kiran Patil

Kiran Patil

Design Engineer

Followers of Kiran Patil519 followers
location of Kiran PatilPune, Maharashtra, India

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  • Timeline

  • About me

    VLSI Lead with FPGA and ASIC expertise

  • Education

    • Sandeepani School of VLSI Design

      2012 - 2013
      Diploma VLSI Design and Functional Verification

      VLSI Design

    • Maharashtra State Board

      2005 - 2006
      10th

    • North Maharashtra University

      2008 - 2012
      Bachelor of Engineering (B.E.) E&TC

      B. Tech.

    • Shivaji University

      2013 - 2015
      Master of Technology (M.Tech.) Electronics Technology

      M. Tech. (Electronics)

  • Experience

    • Bit Mapper Integration Technologies Pvt. Ltd

      Oct 2015 - Apr 2018
      Design Engineer

      Design and develop FPGA based high speed mixed signal electronics systems fordefense application.

    • SMDP-C2SD Meity Govt of India

      May 2018 - Oct 2020
      Lab Engineer

      FPGA prototype and ASIC (RTL2GDS-II) development usign SCL 180nm technology and Cadence Design Tools.

    • Magna International

      Nov 2020 - Jul 2022
      FPGA Engineer

      Design and develop ADAS and Automated driving systems for Automotiveapplications.

    • Wipro

      Jul 2022 - now
      VLSI Lead

  • Licenses & Certifications

    • Conformal Equivalence Checking v21.1 Exam

      Cadence Design Systems
      Feb 2023
      View certificate certificate

    • Fundamentals of IEEE 1801 Low-Power Specification Format v7.0 Exam

      Cadence Design Systems
      Feb 2023
      View certificate certificate

    • VLSI System Designer

      Sandeepani School of VLSI Design
      Jun 2012