Hussein Nili

Experience

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  RFIC Systems Lab - University of Tehran

  Feb 2010 - Jun 2011

  Research Associate / Project Manager

  Design and development of CAD tool packages for layout optimization of on-chip passive elements and interconnects:• Characterization of structural-property dynamics of on-chip passive elements and element via full-wave electromagnetic simulations (IE3D, Sonnet). Development of detailed analytical equivalent circuit models for passive elements and interconnects. • Development of optimum heuristic synthesis algorithms based on partial equivalent circuit models and geometric programming.• Design and implementation of CAD toolboxes for different stages of analysis and optimum design of on-chip interconnects and passive elements. Show less

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  RMIT University

  Jun 2011 - Sept 2018

  Process development for multi-functional complex oxide platforms (resistive switching devices, ferro/piezoelectrics, MEMS/NEMS) and the development and implementation of advanced materials characterization techniques:• Development of the first CMOS-compatible process route for high-performance and scalable nanoionics resistive switching devices based on PVD-synthesized disordered perovskite multilayers (SrTiO3‑x) with excellent analog switching and reliability properties. Identification and implementation of process routes for dopant incorporation towards improving the analog properties. • Development of an accurate nano-contact probing technique based in situ electrical nanoindentation, accounting and calibrating for surface contact area and probe geometric imperfections, capable of probing electrical transport and coupled electromechanical properties down to sub-50 nm resolutions.• Development of controlled synthesis processes for lead-free piezoelectric thin films (KxNa1-xNbO3) and nanostructures for energy harvesting applications, through PVD (sputtering) deposition and post-deposition treatment techniques; allowing for direct control over thin film stoichiometry and microstructure utilizing a single ceramic target. • Extensive materials characterization techniques for stoichiometric and electronic structure properties (XPS, EDX, PL, EELS, etc.), microstructure (XRD, SEM, TEM), and surface and electromechanical properties (AFM, c-AFM, in situ Nanoindentation) to develop and optimize materials and devices process development.• In-depth structure-property characterization for yield, reliability and performance benchmarking. Show less

  • Honorary Associate

    Sept 2015 - Sept 2018

  • Research Fellow

    Mar 2015 - Sept 2015

  • PhD Candidate

    Jul 2011 - Feb 2015

  • Teaching Assistant

    Jun 2011 - Feb 2015
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  Novel Electronic Devices and Computing Systems Lab - University of California Santa Barbara

  Sept 2015 - Sept 2018

  Postdoctoral Scholar

  - CMOS integration of passive analog memristive (RRAM) crossbars• Identifying and solving patterning precursors and alignment issues; development of patterning recipes (for oxide patterning and metallization) for different metal/oxide stacks• Optimizing passive crossbar circuits for operational power, uniformity and yield• Design and development of integrated bipolar linear selectors for 1S1R operation- Development of robust hardware-intrinsic security primitives based on analog NVM arrays• Device optimization and primitive architecture design for improved security and reliability• Development of experimental demos for optimization and benchmarking security primitives- Development of compact SPICE/Verilog-A compatible analytical models for integrated analog metal-oxide memristors- Development of low-power, bio-compatible analog memristive devices for bio-nanoelectronics interfaces• Design and implementation of controlled nanoporous silicon processing (NP-Si) for precise formation of sub-10nm nanoporous layers with control over reaction rate and average nanopore diameter• Process development of multi-layered two terminal memristors based on NP-Si thin film layers Show less

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  GenXComm Inc.

  Sept 2018 - Jul 2019

  Senior Process Engineer
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  Keysight Technologies

  Jul 2019 - now

  Technical Architect / R&D Engineer