Giuseppe Reitano

Experience

• 

  INMOS/Corimme UK

  Sept 1992 - Apr 1993

  Junior CMOS Analog designer

  Developed experience in analogue IPs design for VLSI at INMOS, the Transputer technology world leader, in Bristol UK

• 

  Corimme

  Jan 1993 - Jan 1996

  Analog Designer

  Responsible to provide design rules and signoff criteria to get expected electrical robustness in large CMOS SoCs.

• 

  SGS-Thomson

  Jan 1996 - Jan 2000

  Silicon Project Leader

  Leading the integration of SoC design and IP macros, targeted to the STB, DVD and multimedia market (e.g. TP2, STi5508, STi5518)

• 

  STMicrolectronics

  Jan 2000 - Jan 2004

  SoC signal integrity responsible and analog IP senior consultant

  Responsible to deliver design rules and signoff criteria for CMOS SoC electrical robustness.Consultant of Analog IP architecture, specification and sign-off.Leading a team of analog designers focused to develop tools and sign-off methodologies to achieve "working-first-silicon", shortening time to market and contributing to let ST become top player in the SetTopBox market.

• 

  STMicroelectronics

  Jul 2005 - Mar 2023

  PM in the Automotive Group - Infotainment, GNSS BU EMEA Region key accounts PM of STB Consumer Market. Targeted to follow the programs from the SOW with customers (OEM or operators), allowing them to get full product's maturity on schedule with expected features and quality Managed technical and promotional engineering team, focused to support Marketing and Field Application Engineers in the Emerging Countries Region.

  • Program Manager - PMI PMP® Certified

    Jan 2017 - Mar 2023

  • Program Project Manager

    Jan 2009 - Dec 2016

  • Competence Center Manager

    Jul 2005 - Jan 2009
• 

  Cirrus Logic

  Apr 2023 - now

  Program Manager