Santosh Subramanian

Santosh Subramanian

Internship Project

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location of Santosh SubramanianAustin, Texas, United States

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  • Timeline

  • About me

    RTL Design Engineer

  • Education

    • North Carolina State University

      2021 - 2023
      Master of Science - MS Computer Engineering
    • SSN College of Engineering

      2016 - 2020
      Bachelor of Engineering - BE Electrical and Electronics Engineering
  • Experience

    • Council of Scientific and Industrial Research

      Jan 2020 - Sept 2020
      Internship Project

      I worked as a project intern at the Council of Scientific and Industrial Research on the project titled "Identification of cognitive stress from EEG signals using Autoencoders". Recorded raw EEG signals from Emotiv brain sensor into a .CSV file. Using a 5th order butterworth filter, both EMG and power frequency are removed with lower cutoff frequency as 1 HZ and upper cutoff frequency as 40 HZ. This process is known as cleaning of EEG data. Then an autoencoder is trained and tested. An autoencoder is an unsupervised artificial neural network which learns efficient data coding. To train the autoencoder, some gaussian noise is to be added row wise, so that the autoencoder can be effectively trained to give clean data as the output removing the added noise. Thus the autoencoder learns by itself to automatically remove noise from data and to provide a clean EEG data. Then the autoencoder is tested by feeding an raw unprocessed EEG dataset and observe its efficiency. For identification of cognitive stress, we need to perform feature extraction and classification of the processed EEG data. This is done using a conventional neural network (CNN). The tested CNN can predict the state of mind of the user, but only limited to thinking words like COLLEGE, FRIENDS, LAB, CAT, DOG, and has an accuracy of 88%. Show less

    • NXP Semiconductors

      May 2022 - Aug 2022
      RTL Design Intern
    • Intel Corporation

      Aug 2022 - Jan 2023
      Pre-Silicon Design Verification Intern
    • NXP Semiconductors

      Jun 2023 - now
      Micro-Architecture/RTL Design Engineer

      -µarch implementation, RTL Design and integration of a function_present filter and 32 entry LUT for PCIe IP to route CPU PCIe configuration space access requests to backend software in case of a function miss in LUT-Implemented timeout mechanism to ensure that user software is not blocked out indefinitely from executing other configuration requests if backend software fails to acknowledge a request.-Implemented Messaged Signal Interrupt (MSI) feature to route errors to corresponding event collector -Definition and implementation of register and bit fields for various address spaces (PRB, IERB) and improved register reusability with other PCIe IPs-Identified and resolved input to output timing paths post synthesis to meet timing and area requirements Show less

  • Licenses & Certifications

    • VLSI CAD Part 1: Logic [Honors]

      University of Illinois Urbana-Champaign
      Dec 2020
      View certificate certificate
    • VLSI CAD Part 2: Layout [Honors]

      University of Illinois Urbana-Champaign
      Feb 2021
      View certificate certificate
    • C for Everyone: Programming Fundamentals

      University of California, Santa Cruz
      Mar 2021
      View certificate certificate
  • Honors & Awards

    • Awarded to Santosh Subramanian
      Intel Work Recognition Award Thrilochan S Dec 2022
    • Awarded to Santosh Subramanian
      Intel Work Recognition Award Weizhi Shaun Chua Oct 2022