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Navin Yagnamurthy

Navin Yagnamurthy

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  • Timeline

  • About me

    CPU Validation Manager at NVIDIA

  • Education

    • University of Madras

      1995 - 1999
      Bachelor of Engineering (B.E.) Electronics and Communications Engineering

    • Thayer School of Engineering at Dartmouth

      1999 - 2001
      Master of Science (MS) Electrical Enginering

  • Experience

    • Dartmouth College

      Aug 1999 - Dec 2001

      • Research Associate

        Aug 2001 - Dec 2001

      • Research Assistant

        Aug 1999 - Jul 2001

    • EDA

      Jan 2002 - Apr 2007
      Design Engineer

      Worked on various in-house projects and as a consultant to several southern california companies as part of TIs third party program.

    • Montalvo Systems

      May 2007 - Apr 2008
      Design Engineer

      Worked on developing validation test suite

    • Sun Microsystems

      Apr 2008 - Oct 2008
      MTS

    • NVIDIA

      Nov 2008 - now

      Architecture validationPost-silicon / Accelerated platform based verificationArchitecture modeling and simulationIntegration ArchitecturePerformance verification and simulationSW verification of DCO / hw-sw co-verificationRIS toolsSoC verificationNV-WIT India

      • CPU Validation Manager

        Apr 2013 - now

      • Engineer

        Nov 2008 - now

  • Licenses & Certifications