Experience

• 

  Soliton systems (formerly synthesis corporation)

  Jul 2004 - Jul 2014

  Worked as an architect and tech lead. Led a team of 10 engineers.- Developed the world’s first real-time H.265 hardware encoder IP. Achieved 1080/30p real-time encoding with Arria V FPGA.- Built the H.264 codec IP. Achieved 1080/60p real-time encoding/decoding with 40 nm library.- Built the area-efficient H.264 encoder IP. Achieved 1080/60i real-time encoding with 90 nm library.- Wrote RTL and test bench with Verilog HDL in the projects above.- Utilized Mentor Modelsim and Synopsys Design Compiler. Show less

  • Senior Engineer

    Apr 2009 - Jul 2014

  • Engineer

    Jul 2004 - Mar 2009
• 

  Fixstars corporation（株式会社フィックスターズ）

  Aug 2014 - May 2017

  Senior engineer

  - Created a hardware accelerator to improve storage performance.- Utilized Xilinx Vivado and Intel Quartus Prime to design Zynq-7000, Kintex Ultrascale, and Arria 10.

• 

  ドワンゴ

  Jun 2017 - Mar 2019

  Engineer

  Worked as an architect and tech lead. Led a team of 5 engineers.- Developed the world's first real-time AV1 hardware encoder. Achieved 1080/30p real-time encoding with Stratix 10.- Developed the high-image-quality H.264 hardware encoder.- Wrote RTL and test bench with SystemVerilog in the projects above.

• 

  Leapmind inc.

  Jul 2019 - Jul 2024

  Worked as an architect, tech lead, and manager. Leading a team of 7 engineers.- Developed an energy-efficient DNN accelerator IP "Efficiera".- Achieved 107.8 TOPS/W with 7 nm library.

  • Manager

    Nov 2019 - Jul 2024

  • ASIC/FPGA Design Engineer

    Jul 2019 - Oct 2019
• 

  Tokyo artisan intelligence co., ltd.

  Aug 2024 - now

  - Developing Edge AI Platform "StingRay" on FPGA

  • Manager

    Oct 2024 - now

  • Engineer

    Aug 2024 - Sept 2024