Cameron Morris

Cameron Morris

Brand Coordinator

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location of Cameron MorrisRaleigh-Durham-Chapel Hill Area

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  • Timeline

  • About me

    Applications Engineer at Cadence Design Systems

  • Education

    • North Carolina State University

      2019 - 2023
      Bachelor of Engineering - BE Electrical and Electronics Engineering GPA: 4.0/4.0
  • Experience

    • Feed the Pack Pantry

      Apr 2020 - May 2021
      Brand Coordinator

      Manage and update the Feed the Pack pantry website. Send out the Feed the Pack pantry monthly newsletter containing volunteer opportunities, events, pantry updates, and previous month statistics. Design and create merchandise as well as managing an Amazon Wishlist of pantry food items.

    • ATI Industrial Automation

      Jan 2021 - May 2023
      Electrical Engineering Co-Op

      - Carry out EMC and ESD testing on boards to ensure they are up to standard to continue to be manufactured/sold- Creating, documenting, and implementing testing on new boards in the prototyping stage to better assess functionality of our boards- Worked with engineers in the design and specification phase of products as well as carrying out the development of schematic, placement, and layout of PCBs

    • Feed the Pack

      Jun 2021 - Apr 2023
      Public Relations Coordinator

      - Create, manage, and run all media produced for Feed the Pack, including our website, monthly newsletters, social media accounts, flyers, and other merchandise- Oversee the way other groups use and promote our food pantry's image and likeness- Manage all donor relations and events put on to raise money for Feed the Pack- Cooperate with team members to forge new partnerships and continuing existing partnerships

    • Cadence Design Systems

      Jun 2023 - now
      Application Engineer

      - Develop DFT Design Implementation at the block level using Cadence's Genus and Modus tools- Simulate gate-level netlists using Cadence's Xcelium tool.- Utilize Cadence tool GUIs to debug simulation errors to accurately represent gate-level netlists' static timing analysis

  • Licenses & Certifications

    • Conformal Low-Power Verification v22.1 Exam

      Cadence Design Systems
      Dec 2023
      View certificate certificate
    • Fundamentals of IEEE 1801 Low-Power Specification Format v9.0 Exam

      Cadence Design Systems
      Jul 2023
      View certificate certificate
    • Cerebrus Intelligent Chip Explorer v22.1 Exam

      Cadence Design Systems
      Jan 2024
      View certificate certificate
    • Cadence RTL-to-GDSII Flow v5.0 Exam

      Cadence Design Systems
      Aug 2023
      View certificate certificate
    • Digital IC Design Fundamentals v2.0

      Cadence Design Systems
      Dec 2023
    • Conformal ECO v23.1

      Cadence Design Systems
      Jan 2024
    • Verilog Language and Application v27.0 Exam

      Cadence Design Systems
      Jul 2023
      View certificate certificate
    • Xcelium Simulator v20.09 Exam

      Cadence Design Systems
      Jun 2023
      View certificate certificate
    • Genus Synthesis Solution with Stylus Common UI v22.1 Exam

      Cadence Design Systems
      Jul 2023
      View certificate certificate
    • Tempus Signoff Timing Analysis and Closure with Stylus Common UI v22.1 Exam

      Cadence Design Systems
      Oct 2023
      View certificate certificate
    • Genus Low-Power Synthesis Flow with IEEE 1801 v22.1 Exam

      Cadence Design Systems
      Jul 2023
      View certificate certificate
    • Test Synthesis with Genus Stylus Common UI v22.1 Exam

      Cadence Design Systems
      Jun 2023
      View certificate certificate
    • PE Electrical and Computer: Electronics, Controls, and Communications

      NCEES
      Nov 2023
    • FE Electrical and Computer

      NCEES
      Nov 2022
    • Basic Static Timing Analysis v2.0 Exam

      Cadence Design Systems
      Aug 2023
      View certificate certificate