Jibin Rocha

Experience

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  DRDO, Ministry of Defence, Govt. of India

  Sept 2021 - Jul 2022

  Project Intern

  Worked in a team as part of implementing a target detection algorithm known as Constant False Alarm Rate (CFAR) in an FPGA which is to be used in SONAR Beamforming.

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  Synopsys Inc

  Jul 2022 - Nov 2022

  Technical Engineering

  Worked with iPDK team to develop PyCell codes for the backend structure of PDK mainly for Global Foundries.Practical exposure on working with Synopsys Custom Compiler tool.

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  Maven Silicon

  Jan 2023 - Jan 2024

  Physical Design Trainee

  Gone through the fundamentals of Digital Design, Verilog and various concept CMOS VLSI DesignImplementation and characterization of CMOS logic gates and estimating timing of various Standard cells using Siemens Tanner Tool.Gone through various concepts in Physical Design including Synthesis, Floorplan, Place and Route, CTS and timing closure using various industry standard tools like Synopsys Fusion compiler and Prime Time

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  Tech Mahindra Cerium Pvt Ltd

  Jan 2024 - now

  Physical Design Engineer

  Working on a RISC based Soc from RTL to GDS2 on Intel 18A technology node. Having a deep understanding on Synopsys tools and Reference Methodology (RM) flow. Standalone Physical verification flow creation incorporating several tools such as fusion compiler, calibre for creating merged OASIS, V2LVS for spice netlist extraction and ICV for Layout verification Checks.