Jibin Rocha

Jibin Rocha

Project Intern

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location of Jibin RochaCochin, Kerala, India

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  • Timeline

  • About me

    Physical Design Engineer at Tech Mahindra | Tech file generation | ASIC CAD FLOW | End To End PD Flow | Ex-Synopsys

  • Education

    • Model Technical Higher Secondary School

      2016 - 2018
      Higher Secondary Education 8.8
    • Archbishop Attipetty Public School - India

      2013 - 2016
      High School High School/Secondary Certificate Programs 9.0
    • Model Engineering College

      2018 - 2022
      Bachelor of Technology Electronics and Communication Engineering 8.66
  • Experience

    • DRDO, Ministry of Defence, Govt. of India

      Sept 2021 - Jul 2022
      Project Intern

      Worked in a team as part of implementing a target detection algorithm known as Constant False Alarm Rate (CFAR) in an FPGA which is to be used in SONAR Beamforming.

    • Synopsys Inc

      Jul 2022 - Nov 2022
      Technical Engineering

      Worked with iPDK team to develop PyCell codes for the backend structure of PDK mainly for Global Foundries.Practical exposure on working with Synopsys Custom Compiler tool.

    • Maven Silicon

      Jan 2023 - Jan 2024
      Physical Design Trainee

      Gone through the fundamentals of Digital Design, Verilog and various concept CMOS VLSI DesignImplementation and characterization of CMOS logic gates and estimating timing of various Standard cells using Siemens Tanner Tool.Gone through various concepts in Physical Design including Synthesis, Floorplan, Place and Route, CTS and timing closure using various industry standard tools like Synopsys Fusion compiler and Prime Time

    • Tech Mahindra Cerium Pvt Ltd

      Jan 2024 - now
      Physical Design Engineer

      Working on a RISC based Soc from RTL to GDS2 on Intel 18A technology node. Having a deep understanding on Synopsys tools and Reference Methodology (RM) flow. Standalone Physical verification flow creation incorporating several tools such as fusion compiler, calibre for creating merged OASIS, V2LVS for spice netlist extraction and ICV for Layout verification Checks.

  • Licenses & Certifications

    • Advanced VLSI Physical Design and Verification

      Maven Silicon
      Feb 2024
      View certificate certificate
    • Photonic Integrated Circuits

      Indian Institute of Science - IISc
      Mar 2021
      View certificate certificate