Swetha Deshpande

Experience

• 

  ELECTRONICS CORPORATION OF INDIA LIMITED

  Jun 2016 - Jul 2016

  Intern

  Simulated three designs of carry select adder using Verilog HDL on Xilinx Spartan3 FPGA board. Compared the results of the three designs, CSLA using ripple carry adders, CSLA using BEC converter and CSLA using D-latch. Found CSLA design with D-latch to be the most area efficient and low power design. Design and simulation of 8-bit high speed vedic multiplier and FPGA implementation. Multiplier was designed using Urdhva Tiryagbhyam sutra. Adders using Kogge Stone algorithm were used to generate partial products. Increase in speed and low latency were observed when compared to standard vedic multiplier design. Show less

• 

  AMD

  Jul 2019 - now

  • Sr. Product Development Engineer

    Nov 2022 - now

  • Product Development Engineer 2

    Jul 2019 - Nov 2022