Adit Agarwal

Experience

• 

  Delhi Metro Rail Corporation Ltd

  Jun 2019 - Jul 2019

  Summer Intern
• 

  Cadence Design Systems

  Jul 2021 - Jul 2024

  Worked on MIPI protocol RTL development and verification, specifically for CSI-2 (camera serial interface), DSI-2 (display serial interface) and PHY layer namely D-PHY and C-PHY. Created RTL design for protocols which help in Accelerated Verification through emulation.Integrated PHY layers (D-PHY and C-PHY) with protocols.Architected a C++ layer over RTL code, making it compatible with emulation and prototyping devices, helping customers to easily authenticate code functionality.Debugged customer issues with integration and verification of design. Show less Learned Lint and Clock Domain Crossing (CDC) verification as part of formal sign-off.Created detailed documents/specifications to improve tool functionality, including use of signed and unsigned variables in Verilog code, enhancing customer engagements.Designed test benches to validate functionality of features e.g. custom lint rules and top-down and bottom-up verification for CDC, resulting in enhanced customer engagement.Wrote custom script solutions for a wide range of customers, enabling testing of RTL code. Show less

  • Software Engineer

    Jun 2022 - Jul 2024

  • Formal Verification

    Jul 2021 - May 2022