Joo Hyun (Eric) Park

Experience

• 

  Samsung Electronics

  Jan 1996 - Nov 2017

  Design Methodology Development and Application Engineering of ASIC/SOC design• Application of circuit/gate level timing/power analysis• Development of ASIC/SOC full-chip design verification software• Design automation for high-performance clock design during full-chip integration• Regression systems integration using programming language: static timing analyzer, delay calculator, and many other interface programs for integration and design automation• Got annual Samsung group award in 2000 by recognition of significant development to ASIC/SOC design verification solutions Show less

  • Principal Engineer

    Mar 2014 - Nov 2017

  • Senior Engineer

    Mar 2004 - Feb 2014

  • Software Engineer

    Jan 1996 - Feb 2004
• 

  GlobalFoundries

  Dec 2017 - now

  Senior Member of Technical Staff

  Development and Application Engineering - Design For Manufacturability and Design Profiling • Standardization of CAD flow and design environments • Layout analysis and Machine learning for 12nm, 22nm, and 28nm technology node • Leading OneDeR (common design analysis env. on AWS over fabs ) project of application in Fab1 • Pattern profiling (ADAPT) and similarity analysis of Machine Learning of tape-out products to build database and assess design risk aspect of layout pattern • Layout analysis of FEOL/BEOL as application engineering for FMEA – runset development and tape-out flow integration • Device profiling to correlate model to silicon behavior with 22nm and 28nm test macros • Manufacturability Analysis Scoring (MAS) logic enhancement, DFM recommended rules optimization, leading to improve DFM aware via macros in Place and Routing tech file Show less