Joseph Talia

Experience

• 

  University of California, Berkeley

  Jan 2012 - May 2012

  Undergraduate Researcher

  Berkeley Wireless Research Center

• 

  Intel Corporation

  May 2012 - Aug 2017

  • Design, tested, and finalized tape-out for 6T SRAM arrays used in Intel Integrated GPUs across 7 Intel chip families• Designed the 6T SRAM arrays and control logic while focusing on improving performance, reducing power consumption, and improving density• Executed all design and verification flows necessary for tape-out including Verilog RTL, schematics, formal verification, parasitic extraction, static timing analysis, power analysis, and noise analysis

  • Senior SRAM Circuit Design Engineer

    Apr 2015 - Aug 2017

  • SRAM Circuit Design Engineer II

    May 2014 - Apr 2015

  • SRAM Circuit Design Engineer I

    May 2013 - May 2014

  • SRAM Circuit Design Intern

    May 2012 - May 2013
• 

  Solar Turbines

  Jun 2018 - Sept 2018

  Technical Product Management Intern

  Solar Turbines, a Caterpillar Company• https://blog.rady.ucsd.edu/index.php/2018/10/my-summer-internship-at-solar-turbines/

• 

  Best Buy Health

  Dec 2019 - now

  •Senior Product Manager of the Jitterbug Smart and Lively SIM Card Kit •Product Manager of the Jitterbug Smart, an easy-to-use Android smartphone •Product Manager of the Lively Mobile Plus, a wearable LTE medical alert device

  • Senior Product Manager

    Aug 2023 - now

  • Product Manager

    May 2021 - Aug 2023

  • Associate Product Manager

    Dec 2019 - May 2021