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Jason Wu Chee San

Jason Wu Chee San

location of Jason Wu Chee SanPenang, Malaysia

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  • Timeline

  • About me

    Product Development Engineer at Intel Corporation

  • Education

    • Universiti Malaysia Perlis

      2007 - 2011
      Bachelor of Engineering (B.Eng.) Microelectronics Engineering

      Activities and Societies: Robotics society

    • Universiti Sains Malaysia

      2015 - 2016
      Master of Science (MSc) Microelectronics Engineering

      Advance semiconductor packaging research in Through-Silicon-Via interconnection for high speed and improved functionality for small footprint electronic devices. Multi-stack die (up to 8 stack) interconnect structure evaluation using highly conductive material with different hardness for better structural integrity and strength. EDA simulation for long term reliability and stress assessment of overall multi-die package. Work done lays foundation for future research regarding usage of higher… Show more Advance semiconductor packaging research in Through-Silicon-Via interconnection for high speed and improved functionality for small footprint electronic devices. Multi-stack die (up to 8 stack) interconnect structure evaluation using highly conductive material with different hardness for better structural integrity and strength. EDA simulation for long term reliability and stress assessment of overall multi-die package. Work done lays foundation for future research regarding usage of higher strength, lower material cost but providing similar conductivity characteristic compared to gold for TSV as number of stacks going on upward trend, increasing overall height of semiconductor package. Show less

  • Experience

    • Intel Corporation

      Jul 2011 - now

      System Level Test (SLT) Test development for Programmable Solutions Group (PSG) / Altera next generation Hard Processor System (HPS) IP.Responsibilities:1. HPS IP SLT content development and definition on next generation of PSG/Altera products. - Defined new test method to provide coverage on newly introduced I/O's (USB3, GbE, UHS1 SDIO) with system validation teams. Test defined were eventually used on both SV & SLT.- Involved in cross compilation of ARM architecture based benchmark contents for proper execution on HPS's Linux based operating system.- Created an automation friendly test framework script to ensure test correctly executed and evaluate passing/failing criteria.2. Product sustainability.- Provided SLT support for customer return debugging.- Patched HPS screening method to effectively screen out failures based on customer return debugging learnings. Show less System Level Test (SLT) manufacturing Product Lead for next generation server graphics/AI accelerator segment.Drove a pre-silicon cross-collaboration forum amongst stakeholder teams (functional validation, power & thermal, ATE, binsplit and test automation) to ensure successful SLT enabling during silicon power on. Achieved 96% of STL content enabled and ready for screening on the first week of PowerOn. Lead a team to enable SLT to meet manufacturing goals in terms of cost effectiveness PHIs (test time, stability, retest rate) and yield throughout product milestones. Achieved 100% test coverage/content enabled in Kill-mode by ES2 milestone.Serve as group technical mentor to provide guidance and mentoring PDEs for technical competency growth. Show less

      • Sr. Product Development Engineer

        Apr 2024 - now

      • Sr. Test Development Engineer (PSG)

        Jun 2022 - Mar 2024

      • Product Lead

        Apr 2019 - Jun 2022

      • Sr. Product Development Engineer

        Oct 2014 - Mar 2019

      • Product Development Engineer (HVM)

        Jul 2011 - Sept 2014

  • Licenses & Certifications