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Sergey Shatalov

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Moscow, Moscow City, Russia

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Timeline
About me
Back-end engineer
Education
- Moscow Institute of Electronic Technology (Technical University)
  2003 - 2009
  Master Physics, Nano electronics
- 1151
  1993 - 2003
  Secondary-level education
Experience
- Freescale Semiconductor
  Sept 2007 - Oct 2012
  - Characterization of the I/O and DDK libraries - View generation following views: .lib, Vstorm view, Celtic view, Clarinet view, IBIS view ;- Generation LPE netlists for simulation purposes;- Perl programing (flow automation); - Physical Implementation of digital blocks (RTL to GDSII- BackEnd Design & DRC, LVS Verification & LPE & Spice simulation)- Automation of design stages by Perl and shell;- Engineering specifications writing (SOW);- Participation in real projects:(back-end design of the Ring oscillator block ), (back-end design of the ATC_delay block), (back-end design of the Chip_id and ALL_cells blocks),
  - Characterization and view validation engineer
    Jan 2010 - Oct 2012
  - Back-end engineer
    Sept 2007 - Dec 2009
- Milandr
  Oct 2012 - now
  Lead SoC Back-end engineer at
  Back-end flow implementation of SOC:- Synthesis (JTAG,DFT,OPCG, BSCAN);- Physical implementation (floor-plan,placement,cts,routing,signoff);- SI analysis;- Power analysis;-Verification (DRC LVS LEC).
- Baikal Electronics
  Apr 2022 - now
  Lead Soc ASIC physical design engineer
Licenses & Certifications
- Allegro Sigrity Package Assesment and Model Extraction
  Cadence Design Systems
  Jul 2013
- Cadence QRC User Transistor-level Extraction
  Cadence Design Systems
  Sept 2010
- Low Power Implementation Front End and Back End
  Cadence Design Systems
  Mar 2011