Anshul Jain

Anshul Jain

Content Editor intern

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location of Anshul JainBengaluru, Karnataka, India

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  • Timeline

  • About me

    Senior Engineer at Qualcomm | OMS-CS at Georgia Tech | Ex-Samsung | BITS Pilani

  • Education

    • St. Paul Higher Secondary School, Indore

      2001 - 2015
      High School Mathematics and Computer Science 10/10

      Activities and Societies: Cricket team, Chess team. Secured a perfect 10/10 in CBSE Class X Exam.Recieved a Certificate of merit for excellent academic performance.Appointed as Deputy Sports Secretary in Class 11.

    • Georgia Institute of Technology

      2022 - 2025
      Master of Science - MS Computer Science
    • Birla Institute of Technology and Science, Pilani

      2015 - 2019
      Bachelor’s Degree Electronics and Instrumentation 8.68/10
  • Experience

    • XPrep

      Jul 2016 - Aug 2016
      Content Editor intern

      Development of assignments and quiz papers on topics ranging from class 8 - 12.

    • Madhyansh Regional Association

      Aug 2016 - May 2017
      Executive Committee Member
    • Semi-conductor Laboratory

      May 2017 - Jul 2017
      Summer Research Intern

      Semi-Conductor Laboratory (SCL), an autonomous body under Department of Space, Government of India, is engaged in Research & Development in the area of Microelectronics to meet the strategic needs of the country.-> Learned about the USB module of PIC18F67J50 micro-controller.-> Implemented Hardware interrupts, Device Descriptors and Oscillator Configurations in embedded C language.-> Observed the transfer of various types of packets from the host (PC) to the USB peripheral and vice versa.-> My work can now be extended to USB 3.0 standard. Show less

    • I-PAC (Indian Political Action Committee)

      Jun 2018 - Jul 2018
      Part Time Associate
    • BITS-PILANI

      Aug 2018 - Dec 2018

      Worked as Teaching Assistant for the course 'Electrical Science' at EEE department, BITS Pilani. Responsible for conducting SPICE demo classes (Electrical Science course) for the first year students and help them with their doubts. Worked as a teaching assistant for the course 'Analog and Digital VLSI Design' at EEE department, BITS Pilani. Responsible for providing tutorials of Cadence Virtuoso to the registered students and helping them with their doubts.

      • Teaching Assistant

        Aug 2018 - Dec 2018
      • Teaching Assistant

        Aug 2018 - Dec 2018
    • NVIDIA

      Jan 2019 - Jun 2019
      Intern

      -> Worked on Nvidia's High Speed PHY to make it compatible to System FPGA and emulation.-> Made High Speed PHY model synthesizable by removing and replacing non-synthesizable code.-> Learned about the System FPGA synthesis flow which includes steps from RTL Compilation to System Generate.-> Worked on Synopsys HAPS ProtoCompiler software which helps in FPGA-based prototyping.

    • Samsung Electronics

      Jul 2019 - Nov 2021
      Senior Engineer - Hardware
    • Qualcomm

      Nov 2021 - now
      • Senior Engineer

        Dec 2023 - now
      • Hardware Engineer

        Nov 2021 - now
  • Licenses & Certifications