Experience

• 

  Esilicon

  Jul 2014 - Aug 2015

  Hardware design engineer

  - Functional Operation Verification in TCAM/SRAM- Characterizing Timing and Power for CCS/NLDM- Electro-Migration (EM) and IR Drop Verification

• 

  Ims laboratory

  Sept 2015 - Mar 2018

  Research engineer

  VCO, DLL and PLL design for Frequency Synthesis from System to Transistor Level on ST 28nm FD-SOI

• 

  Stmicroelectronics

  Sept 2016 - Mar 2018

  Research engineer

  Feasibility research for FFT-based Analog Signal Processing as a new RF-Frontend approach for all frequencies/bands Carrier Aggregation (CA) in 5G Receiver. Implementation from System to Transistor level on 28nm FD-SOI with Body-Bias for Power-Performance-Area-Robustness optimization

• 

  Renesas design vietnam co., ltd.

  Jul 2018 - now

  Project Managements and Technical Catch-up for team building and enhancementTiming design from Synthesis to GDS Continuous improvement for Timing ECO flow by Physical Aware/HyperScale and Automatic DFT-SDC verification for PPA. Static Timing Analysis for Ultra-Large-scale IC Design;SDC making with PTC(GCA) and Accuracy checkTiming design approach from Pre-Layout to Timing Closure with Silicon proven.Manual Clock Tree tuning to go from critical timing violations to SignOff success.

  • Manager

    Oct 2024 - now

  • Senior Staff Engineer

    Apr 2023 - Sept 2024

  • Assistant Manager

    Jul 2021 - Mar 2023

  • Staff Engineer

    Jul 2020 - Jul 2021

  • Senior Engineer

    Jul 2018 - Jul 2020