Shane Chen

Shane Chen

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location of Shane ChenHsinchu City, Taiwan, Taiwan

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  • Timeline

  • About me

    SI/PI Deputy Technical Manager

  • Education

    • 中原大學

      2014 - 2016
      M.S. degree Department of Electronic Engineering(APEMC Lab)

      Our lab (APEMC Lab) specializes in PCB signal integrity (SI) and power integrity (PI) research including simulation and measurement.Completed dozens of research topics, and published papers and patents during this two years.M.S. Thesis:多層印刷電路板中藉由通孔連通柱傳輸差模信號之訊號完整性設計 (Signal Integrity Design for A Transition of Differential Signals by Plated Through-hole Vias in Multilayer PCBs)

    • 中原大學

      2010 - 2014
      B.S. degree Department of Electronic Engineering
  • Experience

    • 智邦科技股份有限公司

      Dec 2016 - now

      1. Completed over 60 projects (800/400/100GE, PCIE4/5, DDR4/5, etc.), which encompassed stack-up design, layer planning, trace geometry calculation, BGA fan-out evaluation, 3D structures analysis, PCB-connector co-simulation, and channel compliance confirmation.2. Collaborated with Ansys to develop the application of OptiSLang in the big data analysis process for manufacturing tolerances, while also exploring its advantages and disadvantages and imposing constraints on manufacturers.3. Assumed the role of mentor for new employees in the SI team, guiding them step by step to become proficient engineers capable of independent collaboration with end customers.4. Developed various tools for loss budget calculation, which involved the utilization of class 7/8 PCB materials under different conditions, such as dielectric thickness, glass fabric fiber weave style, copper foil thickness, copper foil weight, oxidation chemical, etc.5. Maintained a good relationship with end customers by completing several quarterly reports, and successfully secured projects by submitting proposals to end customers. Show less 1. Completed over than 40 projects (400/100/40/25/10GE, SATA3, PCIE3/4, DDR3/4, etc… ) including stack-up design, layer planning, trace geometry calculation, BGA fan-out evaluation, 3D structure analysis, channel compliance confirmation.2. Collaborated with Ansys to develop via automated modeling tools and organize big data to build via database.3. Assumed the role of an in-house education and training lecturer within the company, where I conducted four SI education and training courses for layout engineers and HW engineers. These courses covered topics such as basic transmission line theory, reflection theory, waveform observation in frequency domain and time domain, definition and judgment of Setup/Hold time, simulation settings, and layout design constraints, among others.4. Assisted the department manager in completing the process from initial design to actual testing and verification and wrote checklists and created process flowcharts. Show less

      • Deputy Technical Manager

        Jun 2023 - now
      • Sr. SI/PI Engineer

        Sept 2020 - May 2023
      • Adv. SI/PI Engineer

        Aug 2019 - Aug 2020
      • SI/PI Engineer

        Dec 2016 - Jul 2019
  • Licenses & Certifications

    • Power Integrity Analysis and PDN Design

      財團法人自強工業科學基金會
      Aug 2020
    • Matlab basic training

      MathWorks
      Oct 2018
    • Power Integrity Analysis from DC to AC (PowerDC, OptimizePI)

      Graser Technology (Cadence Var)
      Nov 2017
    • Live Training (CEU/PDH)

      IEEE
      Feb 2020
      View certificate certificate
    • Instructor Certificate

      智邦科技
      Jul 2019