Sanket Bahalkar

Experience

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  Instrumentation Forum, BITS Pilani

  Apr 2012 - Apr 2013

  Project Coordinator

  Instrumental role in Projects presented and Mentoring teams for taking part in competitions conducted during APOGEE 2013, all India Inter college Technical festival of BITS Pilani.

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  Canopus Instruments

  May 2012 - Jul 2012

  Internship

  Developed frequency detection application for digital signal using LPC 1752 and KIEL,ensuring frequency recognition below 1 Hz. Comprehensive study of mini-PLC, STG-500 and it implementation in Conveyor Belt Application.

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  Bhabha Atomic Research Centre

  May 2013 - Jul 2013

  Research Intern

  Developed efficient, automated and self checking scanning algorithm for imaging of reactor's core.Expanded saving algorithm by dynamic file handling for storing and retrieving scanned data.Achieved manifold increase in resolution of core's image.

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  STMicroelectronics

  Jan 2014 - Jun 2014

  Project Trainee

  Analyzed Analog Front End - Low Power & High Speed block of MIPI D-PHY architecture and developed automated verification suite for testing in Eldo.Suggested scope of improvements in Slew Rate controlled Transmitter and Input hysteresis circuits of D-PHY architecture and redesigned it for meeting specifications in Cadence Virtuoso.

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  Intel Corporation

  Oct 2014 - Mar 2021

  • Define Subsystem design attributes – Interface requirements, Reset & Clocks, Partitioning for Optimal Synthesis, Power Saving features. • Define Clocking Architecture for Intel Subsystem Methodology, involved working cross teams - Customer SoC's, Global Clock Team & Physical Design team.• Qualify IP’s to be integrated on parameters – Interface, Timing, UPF, Clocks & Reset Domain Crossing and pending bugs. • Ramped up on DFT/DFD network topology for Intel and delivered the DFx network definition for the Subsystem• Enable Physical design teams with multi-million gate count design synthesis and work hand-in-hand for Physical Verification issues. • Facilitate Timing closure and Physical design driven RTL changes ensuring quality RTL delivery.• Support Validation Team on debugs centered around - Connectivity, Isolation, Missing Clocks & Resets. Show less

  • SoC Clocking Engineer

    Sept 2019 - Mar 2021

  • Subsystem uArch Engineer

    Jul 2015 - Aug 2019

  • Physical Design Engineer

    Oct 2014 - Jul 2015
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  NVIDIA

  Mar 2021 - now

  Sr. ASIC Design Engineer