Sia Azad

Sia Azad

Hardware Designer

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location of Sia AzadGreater Malmö Metropolitan Area

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  • Timeline

  • About me

    Electronics engineer

  • Education

    • Kungliga tekniska högskolan / KTH Royal Institute of Technology

      2010 - 2012
      Master of Science - MS System on Chip (ASIC design)
    • Shahid Beheshti University

      2004 - 2009
      B.Sc Electrical Engineering (major in electronics)
    • Tallinn University of Technology

      2014 - 2018
      Doctor of Philosophy - PhD
  • Experience

    • Iran Computer work

      Aug 2006 - Sept 2009
      Hardware Designer

      main responsibilities: Hardware design, PCB design, Embedded System design

    • Pardazesh Samanehaye Paydar

      Jul 2007 - Sept 2007
      Internship Trainee

      Design of a sensor node in a BMS (building management systems) project during internship.

    • Tallinn University of Technology

      Mar 2014 - Jun 2019

      * Design of a Python-based simulator for modeling system level reliability management in NoC based Systems (under horizon2020 project IMMORTAL).* Development of a systematic methodology for design of online hardware assertions (Checkers) along with design of an optimization tool (in Python) for Area/Coverage optimization checkers.* Development of a high-level-testing test pattern optimization tool for MIPS 32 ISA. And a novel method for identifying delay faults in array multipliers.* Design of a wormhole switching Network-on-Chip based MPSoC for an open-source project targeting reliability research. Later integrated in systems resulting in two chip tape-outs (under horizon2020 project IMMORTAL). Show less

      • Researcher

        Sept 2018 - Jun 2019
      • Junior Researcher

        Mar 2014 - Sept 2018
    • ALTEN Sweden

      Jun 2019 - Dec 2023

      * Axis Communication: Maintain also develop new features for Axis camera applications of retail analytics, embedded on a wide range of Axis network cameras. Provide technical customer support for Axis camera applications and data integration software. Take part in the ongoing development of new generation retail analysis application.* European Spallation Source (ESS): focusing on FPGA integration, EPICS development, build system automation and testing of machine protection systems along with system requirement design, and setting up the Scrum management (interim Scrum master) in the team. Show less

      • Business Manager

        Dec 2022 - Dec 2023
      • Consultant

        Jun 2019 - Nov 2022
  • Licenses & Certifications

  • Volunteer Experience

    • Vice-Chair of Tallinn University of Technology Student Branch

      Issued by IEEE on Oct 2015
      IEEEAssociated with Sia Azad