Abhinav Sonkar

Experience

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  Intel Corporation

  Jun 2018 - Mar 2019

  Graduate Technical Intern
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  Vervesemi

  Jun 2019 - Apr 2021

  Digital Design Engineer

  Project Title: - 4 Channel Delta-Sigma ADC IPResponsibilities: -● Worked on RTL of SPI block which supports Asynchronous Interrupt, Synchronous Slave andSynchronous Master configuration along with flexibility to work on variable data size of 16, 24and 32 bit.● Helped in writing constraint file (sdc) for synthesis.Challenges :-● To implement free running serial clock mode in Synchronous Slave configuration by keepingfunctionality intact.● To implement multi device configuration, interfaced in daisy chain fashion, where each devicecan independently work on different configurations.------------------------------------------------------------------------------------------------------------Project Title: - Dual Channel 4GS/s ADC & DAC IPResponsibilities: -● Developed constrained random verification based testbench using System Verilog.● Developed Generator, Driver, Monitor and Coverage from scratch for the verification.● Worked on Digital Mux RTL for both ADC & DAC, which handles data transfer between 2 differentasynchronous clocks (CDC).● Developed synthesizable RTL code for Offset Calibration.● Performed GLS for signing-off.Challenges :-● In implementation of Digital Mux RTL, where data transfer takes place between 2 asynchronousclocks.------------------------------------------------------------------------------------------------------------Project Title: - 8 channel Sigma-Delta ADC IPResponsibilities: -● Developed coverage driven, constrained random verification based testbench using System Verilogfor 8-channel Sigma-Delta ADC.● As part of this project verification plan developed Generator, Driver, Monitor, Coverage fromscratch.● Have developed RTL code for the Sequencer block whose function is to keep switching betweenmultiple active channels and provide control signals for digital filters. It also implements settlingtime required for filters in 8- channel Sigma-Delta ADC.● Performed GLS for signing-off. Show less

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  STMicroelectronics

  Apr 2021 - now

  • Technical Leader

    Apr 2023 - now

  • Senior Design Engineer

    Apr 2021 - Apr 2023