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Wee Chea Chang

Wee chea chang

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  • Timeline

  • About me

    Director of Engineering

  • Education

    • Sekolah menengah sri muar

      -

      Activities and Societies: King Scout Award

    • Open university malaysia

      2021 - 2023
      Master of information technology cgpa 4.00 out of 4.00 (pass with distinction)

    • Universiti teknologi malaysia

      1997 - 2001
      Bachelor of engineering (computer) cgpa 3.86 out of 4.00 (first class honours)

  • Experience

    • Accenture

      Apr 2000 - Jun 2000
      Technical intern

      Commercial website development deploying HTML and Javascript.

    • Intel corporation

      May 2001 - Nov 2017
      Senior staff engineer

      - Verification Architect.- Chaired technical paper reviewing panel of Intel's DTTC Technical Conferences.- Experienced in most of the I/O interfaces and controllers of Intel Chipsets (PCH, MCH, ICH).- Definition and development of VIPs.- Scoreboard framework creator.- Experienced in Intel Chipset's full-chip verification.

    • Mediatek

      Dec 2017 - Feb 2022
      Technical manager

      - DV Lead in the department of Computing and Artificial Intelligence, verifying ARM-based CPU subsystems spanning across most of the state-of-the-art Cortex A-profile CPUs.- Experienced in AMBA interfaces and ARM ecosystem.- Program Manager on DV's Tools, Flows and Methodologies (TFM).- Experienced in pre-silicon Design Verification from RTL to Netlists.- Experienced in post-silicon patterns generation, analysis, debugging and flow automation.- Brought up a DV team specialising in the verification of ARM CPU sub-systems. Show less

    • Arm china

      Mar 2022 - Feb 2023
      Principal engineer

      - Design Verification Leader of the HPC Department.- Delivered fully-verified ARM's Cortex A-profile and M-profile CPU sub-systems and in-house IPs.- TFM

    • Xynthesis pte ltd

      Mar 2022 - Feb 2023
      Principal engineer

      - Design Verification Leader of the HPC Department.- Delivered fully-verified ARM's Cortex A-profile and M-profile CPU sub-systems and in-house IPs.- TFM

    • Adoresys pte ltd

      Feb 2023 - now

      Organisation Bring-up and Expansion, Resource Development & Management, Risk Management, Project Management, Design Verification. Front-end Technical Leader of the company, TFM, Resource Management, Risk Management, Project Management, Design Verification, Verification Architecture, Formal Property Verification, IP-level Verification, CPU Sub-systems, SoC Verification.

      • Director of Engineering

        Mar 2024 - now

      • Technical Director / Senior Principal Engineer

        Feb 2023 - now

  • Licenses & Certifications