Sarmad Paracha

Experience

• 

  Links 2000

  Aug 2019 - Dec 2019

  Calibration Engineer
• 

  Lampró Méllon

  Jan 2020 - Dec 2021

  Methodology and Functional Verification of Quasar. This project was to translate the SweRV EL2 core by Western Digital from System Verilog to Chisel. SweRV EL2 is a 4stage opensource RV32IMCZ core by Western Digital. https://github.com/Lampro-Mellon/Quasar.gitResearch paper on "A comparative study of chisel and system verilog, Based on Logical Equivalent SWERV-EL2 RISC-V Core"

  • Associate Design Engineer

    Oct 2020 - Dec 2021

  • Trainee

    Jan 2020 - Oct 2020
• 

  RapidSilicon

  Dec 2021 - now

  IP PnR Engineer

  Complete block level PnR of IO complex design on 16nm FFC TSMC Technology from RTL to GDS using TSMC standard cells achieving successful tape-in and another project on same design with DTI standard cell library with better PPABuild Custom clock tree to meet certain clock specifications Write out the PDN according to the design floor plan and requirement Write out UPF for design specific power information and declare power sources and power states in the design Perform LEC verification between RTL and Gate Level Netlist and also between RTL and post PnR Netlist Debugging the check route violations and resolving themSignoff Physical Verification of the design by running ICV DRC and LVS, debugging and resolving all the Violations and Layout extraction respectively NDM generation of standard cells and third party Hard macros Achieving local skew and latency spec requirements on 2.5Ghz high frequency different phased clocks by defining clock skew groups and delay insertion SPEF RC extraction of design using StarRC for timing analysis in PrimeTime Perform PT ECOs to achieve timing using PrimeTime Static and dynamic RV analysis using RedHawk tool for early identification of PDN weaknesses and identify RV hot spots in the design Developed a centralized flow for Fusion compiler to be used across team to ensure better project execution and for better tracking during an auditDeveloped Makefile based centralized flows for LEC (formality) and DRC/LVS (ICV), making them push button for all block owners Work with third party vendors to improve the IP quality and meeting the design requirements, for example correct pin orientation and on preferred layer direction, IP size to be certain LCM value Closely work with Third party vendors to improve standard cell library quality by giving necessary feedback, for example reporting unroutable/problematic cells, legalization and PG DRC issues on certain standard cells, reporting problematic boundary corner cells Show less