Bharath Kumar Singh Muralidhar

Experience

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  Cognizant

  Sept 2014 - Sept 2016

  Programmer analyst

  ▶Release Management : Devised tactical, strategic processes across all the functions of release management like planning, designing, scheduling, testing, deploying software applications & upgrades as required by the business.▶User Acceptance Test UAT: Outline precise and accurate User Story acceptancecriteria used by developers, and automation test frameworks to ensure product owner intent is effectively captured.▶Test Management: Collaborate with cross-functional teams to develop a Test-Driven Development (TDD) approach such as a master test plan, test case, test requirements, test scripts, test programs, and test scenarios.▶Tech Modernisation: Responsible for all the activities of OS migration from Unix to Linux & identified, revised the impacted modules by rewriting C, C++ codes, scripts along with defining the suitable test case. Show less

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  Vodafone Chair Mobile Communications Systems

  Oct 2017 - Jul 2018

  Student Assistant
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  CHAIR OF HIGHLY-PARALLEL VLSI SYSTEMS AND NEURO-MICROELECTRONICS

  Jan 2018 - Jul 2018

  Project Student

  ▶Analysis of OpAmp architecture in a 22nm CMOS-Technology

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  GlobalFoundries

  Nov 2018 - Apr 2019

  Student Intern

  ▶Automation: Developed SKILL script to automate schematic and layout to create dynamic test designs improving test coverage & proactively identifying impediments in EMIRV & PEX flows.▶Test Case: Design custom test cases covering both schematic & layout design using cadence virtuoso across different technologies like 22fdx, 28slp, 14lpp and 12 lpp.▶Issue Resolution : Proactively addressed customer issues & supported timely resolution forEMIRV & PEX queries resulting in improving overall customer experience & satisfaction. Show less

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  CHAIR OF HIGHLY-PARALLEL VLSI SYSTEMS AND NEURO-MICROELECTRONICS

  Jul 2019 - Feb 2020

  Master Thesis Student

  ▶Designing a Charge Pump for neurostimulation systems in 22nm

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  Christian-Albrechts-Universität zu Kiel

  Aug 2021 - now

  Scientific Assistant

  ▶Circuit Design: Immaculate expertise in all the development phases from concept to fabrication of analog & digital mixed signal integrated low power circuits using CMOS including schematic entry, simulation, circuit layout & implemented 135,180 & 350 nm for the project "Integrated neural circuits for Tactile Sensing".▶Verification: Astute in defining, planning & executing production/bench-level test plans to assess the functionality, yield &debug a complex, mixed-signal application-specific integrated circuit ( ASIC ) analysis including Parasitics, I/R drop, current analysis, DRC, LVS. ▶Simulation Analysis: Deft in conducting various simulation techniques to explore different design choices, assess the performance & facilitating design optimization and innovation using Motecarlo analysis, IR Analysis, EM Analysis, Process-Voltage-Temperature ( PVT ) corners, Layout Parameter Extraction (LPE).▶Design Expertise: Proven ability in designing low power, low noise highly functional circuits usingsmall-signal analysis, feedback loop theory, noise analysis to mitigate mismatch, linearity & stability.▶AMS: Proficient in the development of robust circuit architecture & layout design for delivering cutting edge highly innovative Analog and Mixed-Signal (AMS) blocks with clear partitioning (IC analog, digital) and IP-based structuring with special focus on dimensioning, simulation & optimization.▶Modelling: Expertise in the development of high-level AMS circuit models like PLL, Oscillator, OP-AMP, Charge Pumps, bandgaps, amplifiers, LDOs, ADCs, DACs, using Verilog, Verilog-A & System Verilog. Show less