Kaushal Buch

Experience

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  EInfochips

  Apr 2005 - Sept 2009

  ASIC Engineer

  Worked on projects related to Digital Design, RTL coding using Verilog HDL,FPGA-based System-on-Chip (SoC) architecture and ASIC IP design, documentation, syn-thesis and timing analysis for FPGA and ASIC designs, functional and gate level verifica-tion of FPGA/ASIC/SoC designs.Projects executed include high-speed video data transfer applications, USB mass storagedevice, hard disc read channel, video switch matrix and ASIC/FPGA IP cores (SPI 4.2, DDR2Memory Controller , I2C bus, BT.656 video interface, NAND Flash memory controller, DMAcontroller)HDL - VerilogTools - Xilinx ISE, NC Verilog, VCS, Actel Libero, Synplify, QuestaSim, ModelSim. Show less

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  Giant Metrewave Radio Telescope, NCRA, Tata Institute of Fundamental Research

  Nov 2009 - now

  Engineer 'F'

  My work involves simulation, design and implementation of signal processing system for real-time radio frequency interference (RFI) mitigation as part of the upgraded GMRT (uGMRT) project. This is the first of its kind to be developed on FPGA and is part of the backend processing system. Currently working towards statistical modeling of different types of RFI and understanding the effects of filtering on astronomical data/imaging.As part of the Expanded GMRT (eGMRT) project, I am working and supervising the development of FPGA-based wideband correlator and multi-beam beamformer. I am also involved in the system-level simulation, analysis of RF and analog baseband processing systems, and development of optimal beamforming algorithms. The current involvement is towards testing this multi-beam beamformer. Have also worked on the development of model-based FPGA designs for digital signal processing system. On the implementation side, I am currently working on Xilinx RF System-on-Chip (RFSoC) platform for realizing a multi-beam beamforming system. Show less